System and method for partitioning a massively parallel computer

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364DIG1, 364229, 36422941, 364230, 364DIG2, 3649494, G06F 15173, G06F 15177

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055617689

ABSTRACT:
A partition establishment arrangement for use in a computer system comprising a plurality of processors interconnected by a communications network. The communications network comprises a plurality of communications nodes connected in a series of levels, with the nodes of at least some of the levels being controllable to connect to multiple ones of the nodes in a subsequent level. The partition establishment arrangement determines the controlling of the communication nodes to facilitate the partitioning of the processors into a plurality of partitions. The partition establishment arrangement, in a plurality of iterations, identifies conflict sets of processors to be assigned to respective partitions at a level, each conflict set identifying partitions for which, at a selected level, a processor may be connected to the same communications nodes in the next level. In each iteration, a level processing portion determines a control value for controlling the communications nodes in response to the conflict sets identified for the level. The operations continue through each of the successive levels.

REFERENCES:
patent: 4644496 (1987-02-01), Andrews
patent: 4925311 (1990-05-01), Neches et al.
patent: 4987536 (1991-01-01), Humblet
Teich et al. "A Transformative Approach to the Partitioning of Processor Arrays", IEEE 1992 pp. 4-20.
Agrawal et al "Partitioning Techniques for Large-Grained Parallelism", IEEE Transacton on Computers, vol. 37, pp. 1627-1634, 1988.

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