System and method for parallel computing multiple packed-sum...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

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07054895

ABSTRACT:
A system and method are presented in which multiple packed-sum absolute differences (PSAD) are computed in response to a single instruction. One embodiment of the system comprises a first register configured to store a first operand having data elements, and a second register configured to store a second operand having data elements. Additionally, the system comprises a processor configured to perform multiple PSAD calculations between the data elements of the second operand and a first subset of data elements of the first operand. The multiple PSAD calculations are performed in response to a single instruction set. One embodiment of the method comprises the steps of receiving a single instruction, and performing multiple PSAD calculations in response to the single instruction.

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patent: 6377970 (2002-04-01), Abdallah et al.
patent: 6526430 (2003-02-01), Hung et al.

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