System and method for packaged memory

Details System and method for packaged memory System and method for packaged memory

2011-01-18

2011-01-18

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230010, C365S189040, C365S233110, C365S189190, C365S201000

Reexamination Certificate

active

07872936

ABSTRACT:
In one embodiment, a memory system is disclosed. The memory system has at least one memory chip having an address and data interface coupled to an internal address and data bus, and a memory controller and interface chip also having a an address and data interface coupled to the address and data interface of the at least one memory chip via an internal address and data bus. The at least one memory chip, the memory controller and interface chip and the internal address and data bus are disposed within a common chip package. The memory controller and interface chip has an external interface configured to be coupled to a standard memory bus via external contacts of the common chip package.

REFERENCES:
patent: 7461199 (2008-12-01), Conley et al.
patent: 2007/0014168 (2007-01-01), Rajan
Qimonda, “HYB18TC1G800C2F HYB18TC1G160C2F 1-Gbit Double-Data-Rate-Two SDRAM DDR2 SDRAM EU RoHS Complaint Products,” Rev. 1.10, Internet Data Sheet, www.quimonda.com, Jul. 2008, pp. 1-63.

Affiliated with

Also associated with

Rating

System and method for packaged memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for packaged memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for packaged memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2619518