System and method for over erase reduction of nitride read...

Details System and method for over erase reduction of nitride read... System and method for over erase reduction of nitride read...

2007-06-19

2007-06-19

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185110, C365S185220

Reexamination Certificate

active

11328941

ABSTRACT:
A nitride read only memory (NROM) erase system is disclosed. The NROM erase system comprises at least one memory sector, N sense amplifiers, and N buffers. The memory sector is segmented into N erase retry units according to the number of the sense amplifiers. One buffer corresponds with one erase retry unit and one sense amplifier. The N buffers are used to indicate whether their corresponding erase retry units are erased after an erase process of an erase operation. One of the buffers will be set if its corresponding erase retry unit is not erased. In this case, a subsequent erase process will begin to erase the un-erased erase retry unit. The erase retry units that are erased in a previous erase process will not be affected by the subsequent erase process. A method for using the NROM erase system is also described.

REFERENCES:
patent: 5473563 (1995-12-01), Suh et al.
patent: 6219280 (2001-04-01), Naganawa
patent: 6385093 (2002-05-01), Bautista, Jr. et al.
patent: 7002850 (2006-02-01), Lin et al.

Affiliated with

Also associated with

Rating

System and method for over erase reduction of nitride read... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for over erase reduction of nitride read..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for over erase reduction of nitride read... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3870796