Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2005-11-01
2005-11-01
Thomas, Tom (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S532000, C438S131000, C438S467000, C438S600000
Reexamination Certificate
active
06960819
ABSTRACT:
A one-time programming memory element, capable of being manufactured in a 0.13 μm or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current, and a switch having a voltage tolerance higher than that of the capacitor/transistor, wherein the capacitor/transistor is one-time programmable as an anti-fuse by application of a voltage across the oxide layer via the switch to cause direct gate tunneling current to thereby rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.
REFERENCES:
patent: 4173791 (1979-11-01), Bell
patent: 4499557 (1985-02-01), Holmberg et al.
patent: 5163180 (1992-11-01), Eltoukhy et al.
patent: 5480828 (1996-01-01), Hsu et al.
patent: 5742555 (1998-04-01), Marr et al.
patent: 5748025 (1998-05-01), Ng et al.
patent: 5834824 (1998-11-01), Shepherd et al.
patent: 5883392 (1999-03-01), Schuegraf
patent: 5949712 (1999-09-01), Rao et al.
patent: 6044012 (2000-03-01), Rao et al.
patent: 6096580 (2000-08-01), Iyer et al.
patent: 6096610 (2000-08-01), Alavi et al.
patent: 6184726 (2001-02-01), Haeberli et al.
patent: 6266269 (2001-07-01), Karp et al.
patent: 6351425 (2002-02-01), Porter
patent: 6515344 (2003-02-01), Wollesen
patent: 6549458 (2003-04-01), Rao et al.
patent: 6836000 (2004-12-01), Marr et al.
patent: 2001/0022746 (2001-09-01), Kim et al.
Shi, Y., et al. “Polarity-Dependent Tunneling Current and Oxide Breakdown in Dual-Gate CMOSFET's”,IEEE Electron Device Letters 19:391-393, (Oct. 1998).
International Search Report for PCT/US01/48853, Issued by the EPO on Jul. 31, 2002.
Schroder, Dieter K., “Semiconductor Material and Device Characterization”, Fig. E6.5(a), Oxide failure modes, John Wiley & Sons, Inc., 2ndEdition, p. 391, (1998).
Schroder, Dieter K., “Semiconductor Material and Device Characterization”, Fig. 6.40, Charge-to-breakdown as a function of oxide thickness, John Wiley & Sons, Inc., 2ndEdition, p397, (1998).
Clark, Lawrence T., “A High-Voltage Output Buffer Fabricated on a 2V CMOS Technology,”Symposium on VLSI Circuits Digest of Technical Papers, pp. 61-62, (1999).
Battacharya Surya
Chen Henry
Chen Vincent
Ito Akira
Shiau Jay
Broadcom Corporation
Diaz José R.
Sterne Kessler Goldstein & Fox P.L.L.C.
Thomas Tom
LandOfFree
System and method for one-time programmed memory through... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for one-time programmed memory through..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for one-time programmed memory through... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3453337