Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2005-04-19
2011-11-08
Donovan, Lincoln (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
Reexamination Certificate
active
08054119
ABSTRACT:
The present invention provides for a method for characterization of pulse-width limiter outputs. A known clock signal is received. A pulse width of the received known clock signal is limited through a first pulse-width limiter to generate a first intermediate signal. The first intermediate signal is delayed by a known amount to generate a first delayed signal. The first intermediate signal is inverted to generate a first inverted signal. A pulse width of the first inverted signal is limited through a second pulse-width limiter to generate a second intermediate signal. The second intermediate signal is delayed by a known amount to generate a second delayed signal. A logic OR operation is performed on the first delayed signal and the second delayed signal to generate a clock out signal.
REFERENCES:
patent: 3586884 (1971-06-01), Gassmann
patent: 3594733 (1971-07-01), Lukens, II
patent: 3594773 (1971-07-01), Cookie et al.
patent: 3638045 (1972-01-01), Hughes
patent: 3831098 (1974-08-01), Fletcher et al.
patent: 4245167 (1981-01-01), Stein
patent: 4305010 (1981-12-01), Wise
patent: 4334243 (1982-06-01), Srivastava
patent: 4881040 (1989-11-01), Vaughn
patent: 5268594 (1993-12-01), Huang
patent: 5309034 (1994-05-01), Ishibashi
patent: 5309456 (1994-05-01), Horton
patent: 5396110 (1995-03-01), Houston
patent: 5566129 (1996-10-01), Nakashima et al.
patent: 5672990 (1997-09-01), Chaw
patent: 5761151 (1998-06-01), Hatakeyama
patent: 5789958 (1998-08-01), Chapman et al.
patent: 5875152 (1999-02-01), Liu et al.
patent: 5929684 (1999-07-01), Daniel
patent: 5969555 (1999-10-01), Suda
patent: 6060922 (2000-05-01), Chow et al.
patent: 6069508 (2000-05-01), Takai
patent: 6084482 (2000-07-01), Nakamura
patent: 6356129 (2002-03-01), O'Brien et al.
patent: 6486722 (2002-11-01), Yamauchi
patent: 6661271 (2003-12-01), Burdick et al.
patent: 6918050 (2005-07-01), Yoshikawa et al.
patent: 6937075 (2005-08-01), Lim et al.
patent: 6973145 (2005-12-01), Smith et al.
patent: 7242233 (2007-07-01), Aipperspach et al.
patent: 7358785 (2008-04-01), Boerstler et al.
patent: 2001/0011913 (2001-08-01), Sher
patent: 2003/0102896 (2003-06-01), Porter et al.
patent: 2005/0010885 (2005-01-01), Aipperspach et al.
patent: 2005/0035801 (2005-02-01), Weiner
patent: 2008/0136480 (2008-06-01), Boerstler et al.
Katz, Randy H.., “Contemporary Logic Design”, , Benjamin/Cummings Publishing Company, Inc. Redwood City CA (1994) pp. 138-139.
Rabaey, Jan M., “Digitalintegrated Circuits—A Design Perspective”, Prentice Hall (1996), Chapter 4, p. 193, Example 4.1.
“A Simplified Method for Limiting Clock Pulse Width” IBM, File Date: Oct. 23, 2003, U.S. Appl. No. 10/692,412, Applicant: Anthony Gus Aippersoach et al.
Boerstler David William
Hailu Eskinder
Qi Jieming
Almo Khareem E
Donovan Lincoln
International Business Machines - Corporation
Talpis Matthew
Walder Jr. Stephen
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