Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-12-09
2004-12-21
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000, C327S206000
Reexamination Certificate
active
06833749
ABSTRACT:
FIELD
The present invention relates to digital circuit design. Specifically, the present invention relates to generating hysteresis in a digital circuit.
BACKGROUND
In the design of digital circuits, the noise immunity of the circuit must be considered. For example, noise in a digital circuit or system can cause a switching circuit to incorrectly transition between logic levels. One of the major contributors to noise occurring on a digital circuit is on-chip generated noise. For example, switching of the output drivers that cause voltage spikes on the power supply buses may produce the on-chip generated noise.
In addition, the operating conditions of the digital circuit can increase or reduce the amount of the generated noise. High noise operating conditions, that is, operating conditions with fast transistor parameters, such as high conductance, high power supply voltages, and low operating temperatures, increase the occurrence of the on-chip generated noise. Conversely, low noise operating conditions, that is operating conditions with slow transistor parameters, such as low conductance, low power supply voltage, and high operating temperatures, reduce the occurrence of the on-chip generated noise.
In order to reduce the negative effects of noise in digital circuits, hysteresis is often employed. Hysteresis typically includes providing a buffer with a degree of noise immunity at the expense of introducing a constant delay into the speed of the digital circuitry. For example, a non-inverting buffer with hysteresis will transition from a first logic state to a second logic state as an input signal applied to the buffer reaches a first switching threshold. To transition the non-inverting buffer from the second logic state back to the first logic state, the input signal causes a transition at a second switching threshold. The first switching threshold is chosen to be closer to the second logic state than the second switching threshold. The difference in the transition points creates hysteresis in the circuit and provides the non-inverting buffer with noise immunity and reduces the occurrence of erroneous switching.
FIG. 1
illustrates a switching circuit
100
with hysteresis. The circuit illustrates a complementary metal oxide semiconductor (“CMOS”) inverter with an input signal applied to an IN
1
terminal
126
. The CMOS inverter includes p-channel metal oxide semiconductor field effect transistors (“MOSFETs”)
104
and
106
coupled to n-channel MOSFETs
108
and
110
. A supply voltage V
DD
terminal
122
is coupled to the source of the p-channel transistor
104
, and a ground voltage V
SS
terminal
124
grounds the source of the n-channel transistor
110
.
A feedback p-channel MOSFET
112
and a feedback n-channel MOSFET
114
are coupled to an n
1
node
120
. The source of the feedback n-channel transistor
114
is coupled to an n
3
node
122
. Further, the drain of the feedback n-channel transistor
114
is coupled to the supply voltage V
DD
terminal
122
, and its gate is coupled to the n
1
node
120
.
Further, the source of the feedback p-channel transistor
112
is coupled to an n
2
node
118
. The drain of the feedback p-channel transistor
112
is grounded by the ground voltage V
SS
terminal
124
, and its gate is coupled to the n
1
node
120
.
A CMOS inverter
116
is coupled to the n
1
node
120
. Although not shown in
FIG. 1
, the CMOS inverter
116
may include a p-channel MOSFET connected in series with an n-channel MOSFET, with the source of the p-channel MOSFET connected to the supply voltage V
DD
terminal
122
, and the source of the n-channel MOSFET grounded by the ground voltage V
SS
terminal
124
.
Considering the switching circuit
100
operation without the effect of the feedback p-channel transistor
112
and the feedback n-channel transistor
114
, when the input signal at the IN
1
terminal
126
transitions from a high level to a low level, the p-channel transistors
104
and
106
are turned on, and a current path is established between the supply voltage V
DD
terminal
122
and the n
1
node
120
. The current supplied by the supply voltage V
DD
terminal
122
increases the voltage of the n
1
node
120
, and the inverter
116
inverts the voltage at the n
1
node
120
. Thus, with a low level input signal applied to the IN
1
terminal
126
, the switching circuit
100
generates a low level output signal at the OUT
1
terminal
128
.
When the input signal at the IN
1
terminal
126
transitions from a low level to a high level, the p-channel transistors
104
and
106
are turned off, and the n-channel transistors
108
and
110
are turned on. A current path is established between the n
1
node
120
and the ground voltage V
SS
terminal
124
. As the current flows to the ground voltage V
SS
terminal
124
, the voltage at the n
1
node
120
decreases. When the voltage level at the IN
1
terminal
126
increases to a high level, the voltage at the n
1
node
120
changes to a low level voltage that is then inverted by the inverter
116
. Thus, with a high level input signal applied to the IN
1
terminal
126
, the switching circuit
100
generates a high level output signal at the OUT
1
terminal
128
.
If the switching circuit
100
does not employ feedback transistors
112
and
114
, and if noise is present in the circuit causing the input signal level to fluctuate during a switching event, an unstable output would be generated at the OUT
1
terminal
128
. To prevent unstable circuit behavior, the source of the n-channel transistor
108
and the drain of the n-channel transistor
110
are controlled by the source voltage of the feedback n-channel transistor
114
. Further, the drain of the p-channel transistor
104
and the source of the p-channel transistor
106
are controlled by the source voltage of the feedback p-channel transistor
112
.
When the input voltage at the IN
1
terminal
126
transitions from a low voltage level to a high voltage level, the p-channel transistors
104
and
106
are turned off, and the n-channel transistors
108
and
110
are turned on. Since the feedback n-channel transistor
114
was already turned on by the previous output signal at the n
1
node
120
(a high voltage signal level at the n
1
node
120
caused by the low input voltage level at the IN
1
terminal
126
), the current flow through the feedback n-channel transistor
114
will slow the discharge from the n
1
node
120
to the ground voltage V
SS
terminal
124
.
Similarly, when the input voltage at the IN
1
terminal
126
transitions from a high voltage level to a low voltage level, the n-channel transistors
108
and
110
are turned off, and the p-channel transistors
104
and
106
are turned on. Since the feedback p-channel transistor
112
was already turned on by the previous output signal at the n
1
node
120
(a low voltage signal level at the n
1
node
120
caused by the high voltage level at the IN
1
terminal
126
), the current flow through the feedback p-channel transistor
112
will slow the charging of n
1
node
120
from the supply voltage V
DD
terminal
122
.
Thus, when the input signal at the input IN
1
terminal
126
transitions from a high voltage level to a low level, hysteresis is provided by the feedback p-channel transistor
112
and, when the input signal at the IN
1
terminal
126
transitions from a low voltage level to a high level, hysteresis is provided by the feedback n-channel transistor
114
.
The prior art circuit illustrated in
FIG. 1
, as well as other commonly used circuits with hysteresis, may be complex as they may include additional circuitry for creating input thresholds that vary depending on the current state of the circuit and, thus, may have circuit areas and power consumption higher that those desired by many applications. Thus, there is an apparent need for a simple and low-power consumption circuit with hysteresis.
REFERENCES:
patent: 5654645 (1997-08-01), Lotfi
patent: 5796281 (1998-08-01), Saeki et al.
patent: 6124733 (2000-09-01), Sharpe-Geisler
patent: 6188244 (200
Honeywell International , Inc.
McDonnell Boehnen & Hulbert & Berghoff LLP
Nguyen Long
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