System and method for minimizing the size of operands

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...

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712898, 708601, G06F 700, G06F 9302

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active

059681659

ABSTRACT:
A dynamic word size processing system which determines for each instruction the number of cycles required by a data path to compute the result. Values in a register file are augmented with additional information which permits a determination of the number of cycles required based on the values in the register file which are referenced by each instruction. A control path combines the information for each register file operand, and computes a value for the additional information to be stored with the result of the instruction.

REFERENCES:
patent: 4258419 (1981-03-01), Blahut et al.
patent: 4424563 (1984-01-01), Lynch
patent: 5053953 (1991-10-01), Patel
patent: 5450605 (1995-09-01), Grochowski et al.
patent: 5689672 (1997-11-01), Witt et al.

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