System and method for minimizing simultaneous switching during s

Details System and method for minimizing simultaneous switching during s System and method for minimizing simultaneous switching during s

1996-07-24

1997-09-02

Canney, Vincent P.

Excavating

H04B 1700

Patent

active

056639660

ABSTRACT:
A system and method for reducing simultaneous switching during scan-based testing of a system logic design. System logic is divided into clusters of system logic, and one or more scan chains are associated with each logic cluster. Each of the logic clusters are concurrently scan tested, yet circuitry in the scan chains associated with a cluster are triggered at different times than the circuitry in the scan chains of other clusters. Offset scan control signals provide the triggering for the scan chains of different clusters. Release and capture functions are also controlled to reduce simultaneous release and capture switching in different clusters.

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patent: 5077740 (1991-12-01), Kanuma
patent: 5321277 (1994-06-01), Sparks et al.
patent: 5606565 (1997-02-01), Edler et al.

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