Data processing: measuring – calibrating – or testing – Calibration or correction system – Circuit tuning
Reexamination Certificate
2001-06-28
2003-06-17
Shah, Kamini (Department: 2863)
Data processing: measuring, calibrating, or testing
Calibration or correction system
Circuit tuning
C365S194000, C327S241000
Reexamination Certificate
active
06581017
ABSTRACT:
FIELD
The invention relates to a system and method for minimizing delay variation between multiple double data rate strobes. More particularly, the present invention enables the calibration of circuits used to transfer data from memory to a memory controller upon system startup to control for on-die variations in the circuits and to periodically re-calibrate the circuits to compensate for voltage and temperature variations seen during operation of the circuit with minimal interference in the normal transfer of data from memory to the memory controller.
BACKGROUND
In the rapid development of computers many advancements have been seen in the areas of processor speed, throughput, communications, and fault tolerance. Microprocessor speed is measured in cycles per second or hertz. Today=s high-end 32-bit microprocessors operate at over 1.7 Ghz (gigahertz), 1.7 billion cycles per second, and in the near future this is expected to go substantially higher 2.6 and 3.3 Ghz and beyond. At this sort of cycle speed a clock would have to generate a pulse or cycle at least ten times each billionth of a second and usually significantly faster.
With processors operating at such higher rates it is necessary to supply data to the processor when required from memory at a comparable rate otherwise a bottle neck is formed and the processor spends much of its time waiting for data.
One method, as shown in
FIG. 1
, utilized to improve the transfer rate of memory utilizes Double Data Rate (DDR) devices to transfer data at both the leading edge of a clock cycle and the trailing edge of the clock cycle. These DDR devices have a source-synchronous clocking protocol to transfer data from the memory to the memory controller. Data (DQ)
110
from memory is captured by the memory controller using a clock (DQS)
100
supplied by the memory devices. However, in order to avoid DQ
110
errors which may occur when the DQS
100
signal levels change, each DQS
100
from memory is delayed, as shown in
FIG. 1
in the delayed DQS
120
signal, so that data can be clocked in the center of the valid data window. The precision of the strobe delay
130
is important because any variation in the strobe delay
130
translates into added setup/hold time for the memory controller. If the setup/hold time is too large, the system becomes unworkable. This is especially true as DDR technology moves to faster speeds.
There are several methods available to generate a precise delay. Most all of these methods involve a delay element that can be calibrated to a precise delay for the DQS
100
signal. The calibration adjusts controls in the delay element so that a precise delay strobe
130
can be given regardless of the microcircuit process parameters, temperature, and voltage. How these delay strobes
130
are calibrated will determine how much variation can occur.
One method employed to calibrate the delay strobe
130
uses a master/slave approach where a master delay element is continuous calculating the control settings needed by the slave delay elements. The master is never used to delay actual strobes from the DDR devices because it is used exclusively for updating the slave delay element controls. The slaves are used for the actual strobe delay, but are never used for calibration since that it would reduce availability for memory transactions. This creates a problem if there is on-die variation that causes the characteristics of the master delay element to be different from that of the slave delay element. The master may be precisely set to the desired delay but the slaves can vary enough to cause a problem for higher speed DDR devices.
One solution to this problem would be to calibrate each delay line individually without a master/slave scheme. On-die variation in process parameters would be taken into account as well as the current voltage and temperature giving a precise delay. However, the voltage and temperature of the delay line will change as the circuit is operated and the delay will no longer be at the precise delay that is needed by the DDR device. To compensate for this, periodically the delay elements could be re-calibrated to the correct control setting, but this would prevent memory read transactions from occurring during re-calibration. If temperature and voltage vary frequently, it may be necessary to do more calibrations, which will further reduce the availability to memory which reduces performance of the system.
Therefore, what is needed is a system and method in which the delay strobe
130
be calibrated to take into consideration on-die variations in individual circuits as well as variations which occur due to changes in voltage and temperature. This system and method should have minimal, if any, impact in transfer operations to and from memory.
REFERENCES:
patent: 6292097 (2001-09-01), Tewell
patent: 6316980 (2001-11-01), Vogt et al.
patent: 6456544 (2002-09-01), Zumkehr
Intel Corporation
Shah Kamini
LandOfFree
System and method for minimizing delay variation in double... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for minimizing delay variation in double..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for minimizing delay variation in double... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3140419