Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Reexamination Certificate
1999-09-30
2002-09-17
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
C709S216000, C711S141000, C711S145000, C711S152000, C711S219000
Reexamination Certificate
active
06453408
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of computer memory systems, and more particularly to a system and method for memory page migration in a multiprocessor computer.
BACKGROUND OF THE INVENTION
Multiprocessor computers often include a large number of computer processors that may operate in parallel. One example of parallel processing computer architecture is Cache-Coherent multiprocessors with Non-Uniform Memory Access (ccNUMA) architecture. Non-Uniform Memory Access (NUMA) architecture is a type of parallel processing architecture in which each processor has its own local memory but can also access memory owned by other processors. The parallel processing architecture is referred to as non-uniform because memory access times are faster when a processor accesses its own local memory as compared to when a processor borrows memory from another processor.
Cache-coherent multiprocessors with non-uniform memory access have become quite attractive as computer servers for parallel applications in the field of scientific computing. These multiprocessor computers combine scalability with a shared memory programming model thereby discharging the applications designer from data distribution and coherency maintenance. Cache locality, load balancing and scheduling remain of crucial importance. Large caches used in scalable shared memory architectures can avoid high memory access times if data is referenced within the address scope of the cache. Locality is the key issue to multiprocessor performance. In other words, the closer the memory is to a processor that accesses that memory, the faster the access times. This translates to enhanced multiprocessor computer performance.
Some multi-processing computer architectures provide for movement of memory pages such that memory pages are moved close to the processors that access those memory pages. Current systems for memory page movement, or page migration, have incurred excessive overhead that negatively impacts multiprocessor computer performance. Therefore, it is desirable to provide a more efficient manner of handling page migration within a multiprocessor computer.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated that a need has arisen for a system and method for memory page migration in a multiprocessor computer that provides more efficient memory page migration. In accordance with the present invention, a system and method for memory page migration in a multiprocessor computer are provided that substantially eliminate and reduce disadvantages and problems associated with conventional memory page migration techniques.
According to an embodiment of the present invention, a method for controlling memory page migration in a parallel processor computer is provided that includes requesting access to a memory page by a requester processor. The method next determines whether the requester processor is a local processor or a remote processor. The method then either increments a local access counter in response to the requester processor being a local processor or increments a remote access counter in response to the requester processor being a remote processor. The access counter that was incremented is then referred to as an incremented counter. The method then sets a threshold processing indicator to a positive value in response to the incremented counter being greater than or equal to a value threshold. The method then generates a system interrupt in response to a positive threshold processing indicator.
In another embodiment of the present invention, the method for controlling memory page migration also includes computing a difference between the local access counter and the remote access counter and then setting the threshold processing indicator to a positive value in response to the difference being greater than or equal to a difference threshold. In yet another embodiment of the present invention, the method for controlling memory page migration in a parallel processor computer described above is performed with every Nth access to the memory page. A page access counter tracks a number of accesses to the memory page. When the page access counter reaches N, the page counter is initialized with the zero and the method for controlling memory page migration is performed.
The present invention provides various technical advantages over conventional page migration techniques. For example, one technical advantage is that only two counters are used. for each memory page thereby reducing overhead associated with previous page migration techniques which used a counter for each parallel processor in each memory page. Another technical advantage is that the page migration technique checks for a page migration situation with every Nth access to the memory page thereby reducing overhead associated with the page migration technique. Other technical advantages may be readily apparent to one skilled in the art from the following figures, description, and claims.
REFERENCES:
patent: 5237673 (1993-08-01), Orbits et al.
patent: 5269013 (1993-12-01), Abramson et al.
McCracken David Edward
Stuart Fiske James A.
Widra Leonard Mark
Baker & Botts L.L.P.
Pan Daniel H.
Silicon Graphics Inc.
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