System and method for memory array decoding

Details System and method for memory array decoding System and method for memory array decoding

2011-08-23

2011-08-23

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189040, C365S189190

Reexamination Certificate

active

08004926

ABSTRACT:
A memory system includes Q memory blocks that each include M memory sub-blocks. The memory system also includes Q word line decoders that each are associated with a different one of the Q memory blocks. The memory system also includes a bit line decoder and Q×M switch modules. Each Q×M switch module selectively controls access to up to J of the M memory sub-blocks of the Q memory blocks. The Q word line decoders and the bit line decoder access less than M memory sub-blocks in at least two of the Q memory blocks during one of a read and write operation. M and Q are integers greater than 1, and J is an integer greater than or equal to 1.

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International Search Report for International Application No. PCT/US2009/033040, mailed May 19, 2009.

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