Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-06-28
2004-03-30
Pert, Evan (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S750010
Reexamination Certificate
active
06714035
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention generally relates to integrated circuits. More particularly, and not by way of any limitation, the present invention is directed to a system and method for measuring fault coverage in an integrated circuit.
2. Description of Related Art
The evaluation of the reliability and quality of a digital integrated circuit (IC) comprises several distinct testing phases including a verification phase, a parametric testing phase and a defect testing phase. The verification testing phase is the initial phase in which the first prototype chips are tested to ensure that they match their functional specification, that is, to verify the correctness of the design. The verification testing phase checks that all design rules are adhered to, from layout to electrical parameters. The parametric testing phase ensures components meet design specification for delays, voltages, power, etc.
The defect testing phase ensures that only defect-free production chips are packaged and shipped. The defect testing phase involves testing for a relatively large number of different physical defects that could be present. These physical defects may be classified by their logical fault effect on the functionality of the circuit. For example, permanent faults are physical defects which exist long enough to be observed. Temporary faults are physical defects which appear and disappear in short intervals of time. Delay faults are physical defects which affect the operating speed of the circuit. Sequential faults are physical defects which cause a combinational circuit to behave like a sequential circuit and occur in only certain technologies (e.g. CMOS).
One of the most practical methods for defect testing is to employ a fault model of the physical defects that can occur in the IC at a high level of abstraction, typically the logic level, and then develop algorithms, commonly referred to as Functional Test Vector (FTV) sets, for the modeled faults. Depending on the fault model and quality of the functional test vector set, the functional test vector set may cover a high percentage of the actual physical defects. The percent of all possible internal faults in an IC that are observable by the FTV set employed is referred to as the fault coverage. In general, the more robust and reliable fault models and associated FTV sets provide greater fault coverage.
Processes for automated fault testing of large scale integrated circuits commonly employ what is known as a “stuck-at” fault model to emulate permanent faults that may occur during fabrication of the integrated circuit under test. In this model, the circuit description is modified or otherwise rendered to correspond to a stuck-at fault state, i.e., a continuous logic state of 0 or 1. In a process known as fault simulation, the test vector sets developed based on the stuck-at fault model are applied to the IC and the value of the corresponding response is compared to the expected response value. After many faults are simulated and multiple test vectors run, an indication of the fault coverage of the applied test vector set is provided. If the fault coverage is unacceptably low, the test vector set may be modified to exercise portions of the circuit where undetectable faults lie.
Typically, fault coverage is measured via software fault simulations. In software fault simulations, a model of the IC is seeded with stuck-at faults and the functional test vector sets are run. This simulation is repeated thousands of times, seeding a different fault each time, to determine fault coverage.
It has been found, however, that as the size and complexity of ICs continues to grow, the software fault simulations do not provide fast and effective measurements of fault coverage. Moreover, software simulations provide a theoretical, not empirical, indication of fault coverage. Therefore, a need exists for a system and method for measuring fault coverage that is robust enough for today's production cycles that include ICs of ever-growing size and complexity. Additionally, a need exists for a system and method for measuring fault coverage that provides empirical data.
SUMMARY OF THE INVENTION
Accordingly, the present invention advantageously provides a system and method for measuring fault coverage that overcomes these and other drawbacks and deficiencies of the state-of-the art fault coverage solutions. The fault coverage scheme of the present invention provides for robust fault coverage measurement that is fast enough to be applied to the large amount of chips in today's production cycles that include ICs of ever-growing size and complexity. Moreover, an empirical measurement of fault coverage of actual devices is provided rather than a theoretical estimate.
The system includes a Device Under Test (DUT) assembly having an IC that includes at least one node, a probe, and a test pattern generator and interface system. The DUT's IC is operable to be stimulated to a stuck-at fault condition when stimulated by a certain frequency of electromagnetic (EM) radiation. The probe is operable to stimulate the DUT assembly with the certain frequency of EM radiation to create a temporary stuck-at-zero or stuck-at-one condition. The test pattern system generator and interface system interfaces with the DUT assembly to provide a test vector to the DUT and receive a corresponding response which is indicative of a fault coverage measurement.
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Micaela Serra, Dept. of Computer Science, Univ. of Victoria, Victoria, B.C. Canada; “Digital IC Testing: An Introduction”; undated; 10 pages.
Hewlett--Packard Development Company, L.P.
Nguyen Tung X.
Pert Evan
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