System and method for matching data and clock signal delays...

Details System and method for matching data and clock signal delays... System and method for matching data and clock signal delays...

2007-03-20

2007-03-20

Tran, Khai (Department: 2611)

Pulse or digital communications

Synchronizers

Network synchronizing more than two stations

C327S094000, C365S194000

Reexamination Certificate

active

10046597

ABSTRACT:
A system and method for providing a clock signal and data signal delay match to improve setup and hold times for integrated circuits is disclosed. In a simplified embodiment, the system comprises a clock receiver capable of removing noise from a received clock signal. A clock buffer is connected to the clock receiver and is capable of driving the received clock signal to a register. A data receiver is located within the system which is capable of removing noise from received data. In addition at least one miniature clock buffer is located within the system, wherein the at least one miniaturized clock buffer is a scaled version of the clock buffer having a scaling factor of K, the scaling factor representing a number of miniature clock buffers utilized to minimize negative variations experienced by the clock buffer.

REFERENCES:
patent: 5157277 (1992-10-01), Tran et al.
patent: 6104251 (2000-08-01), Ramey et al.
patent: 6240524 (2001-05-01), Suzuki
patent: 6532544 (2003-03-01), Masleid et al.
patent: 6788754 (2004-09-01), Liepe
patent: 2002/0023253 (2002-02-01), Pasqualini
patent: 2002/0118563 (2002-08-01), Keeth et al.
patent: 2002/0154718 (2002-10-01), Fong et al.

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