Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
2001-05-03
2003-06-03
Picard, Leo (Department: 2125)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S121000, C705S002000
Reexamination Certificate
active
06574521
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to systems and methods for managing work-in-process (WIP) workload within fabrication facilities. More particularly, the present invention relates to systems and methods for efficiently managing work-in-process (WIP) workload within fabrication facilities.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, so also has increased the complexity of microelectronic fabrication processing methods and microelectronic fabrication processing facilities which are employed for fabricating microelectronic fabrications. The increased complexity of microelectronic fabrication processing methods and microelectronic fabrication processing facilities which are employed for fabricating microelectronic fabrications derives in-part from: (1) the length (i.e., total number of process steps) of a typical microelectronic fabrication process description; along with (2) the variety of microelectronic fabrication process tools which is typically employed for fabricating a typical microelectronic fabrication; further in conjunction with (3) the variety of individual microelectronic fabrications (i.e., part numbers) which is typically fabricated within a typical microelectronic fabrication processing facility; still further in conjunction with (4) any specific microelectronic fabrication tool routing requirements which may be encountered when fabricating a particular microelectronic fabrication or a particular class of microelectronic fabrications within either a single microelectronic fabrication processing facility or a plurality of microelectronic fabrication processing facilities.
Further contributing to the complexity of microelectronic fabrication processing methods and microelectronic fabrication processing facilities is the generally distributed (i.e., nonlinear) nature of microelectronic fabrication processing methods and microelectronic fabrication processing facilities, which further allows for various production priorities and dispatching rules when fabricating multiple microelectronic fabrication part numbers within either individual microelectronic fabrication processing facilities or multiple microelectronic fabrication processing facilities. Such varied production priorities and dispatching rules in-turn often provide difficulties in management of microelectronic fabrication work-in-process (WIP) workload within microelectronic fabrication processing facilities.
In light of the foregoing, it is thus desirable in the art of microelectronic fabrication to provide systems and methods for efficiently managing microelectronic fabrication work-in-process (WIP) workload within microelectronic fabrication facilities.
It is towards the foregoing object that the present invention is directed.
Various systems and methods have been disclosed in the arts of manufacturing and fabrication for managing fabrication workload within fabrication facilities, such as but not limited to microelectronic fabrication work-in-process (WIP) workload within microelectronic fabrication facilities.
For example, Weng, in U.S. Pat. No. 5,612,886, discloses a system and a method for managing, with enhanced efficiency, semiconductor integrated circuit microelectronic fabrication work-in-process (WIP) workload within a semiconductor integrated circuit microelectronic fabrication facility. To realize the foregoing object, the system and the method employ a dynamic dispatching algorithm which in turn employs a sorting of semiconductor integrated circuit microelectronic fabrication work-in-process (WIP) workload by both priority and queue time, and further wherein the dynamic dispatching algorithm incorporates both semiconductor substrate release rules and semiconductor integrated circuit microelectronic fabrication dispatch rules.
In addition, Pan et al., in U.S. Pat. No. 5,748,478, disclose a system and a method for optimizing output workload of a fabrication facility, such as but not limited to a semiconductor integrated circuit microelectronic fabrication facility. To realize the foregoing object, the system and the method provide, in general, for determining a work-in-process (WIP) workload inflow within the fabrication facility, for determining a work-in-process (WIP) workload output within the fabrication facility and for calculating a work-in-process (WIP) workload flow intensity within the fabrication facility.
Further, Chin et al., in U.S. Pat. No. 5,818,716, also disclose a system and a method for managing, with enhanced efficiency, work-in-process (WIP) workload within a fabrication facility, such as but not limited to semiconductor integrated circuit microelectronic fabrication work-in-process (WIP) workload within a semiconductor integrated circuit microelectronic fabrication facility. To realize the foregoing object, the system and the method employ a required turn rate (RTR) algorithm which determines not only a due date and a production priority for the work-in-process (WIP) workload within the fabrication facility, but also provides for local dispatching of the work-in-process (WIP) workload within the fabrication facility.
Still further, Dangat et al., in U.S. Pat. No. 5,971,585, discloses a method for optimizing within a fabrication facility, such as but not limited to a microelectronic fabrication facility, fabrication assets with respect to fabrication demands, such as to determine which fabrication demands may be met, and thus manage a workload within the fabrication facility. To realize the foregoing object, the method employs a best can do (BCD) algorithm for matching the fabrication assets with respect to fabrication demands, where the best can do (BCD) algorithm comprises a forward implode feasible plan solver which may alternatively employ either heuristic decision technology or linear programming decision technology.
Finally, Chacon, in U.S. Pat. No. 6,128,588, discloses a system and a method for optimizing within a microelectronic fabrication facility, and in particular within a semiconductor integrated circuit microelectronic fabrication facility, operation of the microelectronic fabrication facility, and in particular the semiconductor integrated circuit microelectronic fabrication facility. To realize the foregoing object the system and the method employ, in addition to a microelectronic fabrication facility manufacturing execution system (MES) system, a correlating microelectronic fabrication facility scheduling simulation system.
In addition, and although not specifically directed towards systems and methods for efficiently managing work-in-process (WIP) workload within fabrication facilities, DeJule, in “Mix-and-Match: A Necessary Choice,” Semiconductor International, February 2000, pp. 66-67, discusses a continuing object and trend with respect to advanced semiconductor integrated circuit microelectronic fabrication of continued decreases in overlay tolerances within advanced semiconductor integrated circuit microelectronic fabrications. To realize the foregoing object, it is typically desirable within the art of advanced semiconductor integrated circuit microelectronic fabrication when fabricating advanced semiconductor integrated circuit microelectronic fabrications to route individual semiconductor integrated circuit microelectronic fabrication work in process (WIP) workload lots through identical photolithographic fabrication tools or matched photolithographic fabrication tools for each of multiple sequential photolithographic processing steps employed when fabricating advanced semiconductor integrated circuit microelectronic fabrication work-in-process (WIP) workload lots.
Desirable in the art of microelectronic fabrication are additional systems and meth
Lee Douglas S.
Picard Leo
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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