System and method for managing queue read and write pointers

Details System and method for managing queue read and write pointers System and method for managing queue read and write pointers

1994-08-22

1995-10-17

Rudolph, Rebecca L.

Boots, shoes, and leggings

395292, 39549701, 395872, 364DIG1, 3642396, 3642443, 364245, 3642456, 3642545, G06F 932, G06F 1312

Patent

active

054598397

ABSTRACT:
A queue pointer manager contained in an integrated data controller is capable of controlling high speed data transfers between a high speed controlled data channel, a local processor bus and a dedicated local data bus. The overall design utilizes enhanced features of the Micro Channel architecture and data buffering to achieve maximum burst rates of 80 megabytes and to allow communications with 8, 16, 32 and 64 bit Micro Channel devices. Queued demands allow flexible programming of the Micro Channel master operations and reporting of completion statuses. The hardware control of command and status queuing functions increases the processing speed of control operations and reduces the need for software queuing. Extensive error checking/reporting, programming parameters, internal wrap self-test capability give the integrated data controller advanced functions as an input/output processor. The queue pointer manager also manages queue read and write pointers.

REFERENCES:
patent: 4507760 (1985-03-01), Fraser
patent: 4682284 (1987-07-01), Schrofer
patent: 4807111 (1989-02-01), Cohen et al.
patent: 4816996 (1989-03-01), Hill et al.
patent: 4878166 (1989-10-01), Johnson et al.
IBM TDB, vol. 24, No. 6 to Conroy, entitled "Hardware/Microcode Support Of Queuing", Nov. 1981, pp. 2716-2723.

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