Coded data generation or conversion – Sample and hold – Sampled and held input signal with linear return to datum
Reexamination Certificate
2007-09-25
2007-09-25
Mai, Lam T. (Department: 2819)
Coded data generation or conversion
Sample and hold
Sampled and held input signal with linear return to datum
C341S122000
Reexamination Certificate
active
11282265
ABSTRACT:
A system and method for processing sample data employing hardware, such as a Field Programmable Gate Array (FPGA), to process the sample data in small pipelined steps. The processing includes a circular buffer where the read and write of data is synchronous, preventing buffer overrun or data loss. This pipeline processing approach allows increasing data acquisition channels or additional processing steps without limiting processing speed.
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International Search Report, PCT/US2005/041701, mailed Apr. 10, 2006.
Daffer McDaniel LLP
Huston Charles D.
Lettang Mollie E.
Luminex Corporation
Mai Lam T.
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