System and method for managing data from a flow analyzer

Coded data generation or conversion – Sample and hold – Sampled and held input signal with linear return to datum

Reexamination Certificate

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C341S122000

Reexamination Certificate

active

11282265

ABSTRACT:
A system and method for processing sample data employing hardware, such as a Field Programmable Gate Array (FPGA), to process the sample data in small pipelined steps. The processing includes a circular buffer where the read and write of data is synchronous, preventing buffer overrun or data loss. This pipeline processing approach allows increasing data acquisition channels or additional processing steps without limiting processing speed.

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patent: 6658357 (2003-12-01), Chandler
patent: 6809804 (2004-10-01), Yount et al.
patent: 2317228 (1998-03-01), None
International Search Report, PCT/US2005/041701, mailed Apr. 10, 2006.

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