System and method for low power wordline logic for a memory

Details System and method for low power wordline logic for a memory System and method for low power wordline logic for a memory

2006-04-11

2008-12-16

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S227000

Reexamination Certificate

active

07466620

ABSTRACT:
A method of reducing power consumption of a memory is provided. A request is received to access a memory device, including a decoder, a plurality of wordline drivers and a plurality of wordlines. Each wordline is associated with a wordline driver of the plurality of wordline drivers. The request is decoded by a decoder to determine an address associated with the request. A wordline driver of the plurality of wordline drivers is selectively powered to access the address of the memory device, where the wordline driver is associated with a particular wordline of the plurality of wordlines that is related to the address bits, without powering other wordlines of the plurality of wordlines.

REFERENCES:
patent: 5408144 (1995-04-01), Sakata et al.
patent: 2004/0155314 (2004-08-01), Sakata et al.
patent: 2004/0252574 (2004-12-01), Jamshidi et al.
patent: 2005/0146972 (2005-07-01), Hong

Affiliated with

Also associated with

Rating

System and method for low power wordline logic for a memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for low power wordline logic for a memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for low power wordline logic for a memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4022631