Electrical computers and digital processing systems: multicomput – Computer-to-computer direct memory accessing
Reexamination Certificate
2007-03-20
2007-03-20
Maung, Zarni (Department: 2155)
Electrical computers and digital processing systems: multicomput
Computer-to-computer direct memory accessing
C709S201000, C709S214000, C711S200000, C711S202000, C711S220000, C711S221000
Reexamination Certificate
active
10154100
ABSTRACT:
A system and method for passing messages between domains with low overhead in a multi-node computer system. A CPU node in a sending domain issues a request to a memory node in a receiving domain using memory-mapped input/output window. This causes the message to be transmitted to a coherent space of the receiving domain. All messages are cache-line in size. A small portion of each cache line, cyclic counter field, is overwritten before the cache line is written in the coherent address space of the receiving domain. A massaging driver polls the cyclic count field of the cache line in the processor cache to determine when the next message is written in the coherent address space of the receiving domain. This allows the CPU to detect when the last received message is written into the coherent address space of the receiving domain without generating transactions on CPU interface.
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Conway Patrick N.
Farrell Jeremy J.
Masuyama Kazunori
Miryala Sudheer
Shimizu Takeshi
Fenwick & West LLP
Korobov V.
Maung Zarni
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