System and method for limiting exposure of hardware failure...

Details System and method for limiting exposure of hardware failure... System and method for limiting exposure of hardware failure...

2011-04-26

2011-04-26

Kindred, Alford W (Department: 2181)

Electrical computers and digital processing systems: processing

Architecture based instruction processing

Reexamination Certificate

active

07934076

ABSTRACT:
A method and apparatus for limiting the exposure of hardware failure information is described. In one embodiment, an error reporting system of a processor may log various status and error address data into registers that retain their contents through a warm reset event. But the error reporting system of the processor may then determine whether the processor is operating in a trusted or secure mode. If not, then the processor's architectural state variables may also be logged into registers. But if the processor is operating in a trusted or secure mode, then the logging of the architectural state variables may be inhibited, or flagged as invalid.

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