System and method for intersample timing error reduction

Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Frequency of cyclic current or voltage

Reexamination Certificate

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C324S076240

Reexamination Certificate

active

06614216

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention is related generally to the timing of sampling intervals in a system for monitoring occurrences, events, or quantities, and more particularly to a system and method for reducing or minimizing intersample timing error in such applications.
While the invention may find other applications, the invention will be illustrated and described herein with reference to the specific problem of minimizing or eliminating a mismatch between the system clock and the frequency of the signal being measured in a power metering system which monitors voltages and currents at grid frequencies, such as 50 Hz or 60 Hz frequencies, or the like.
Using crystal oscillators or other oscillators at standard “off the shelf” frequencies has been noted to produce residual sampling errors or intersample timing errors when measuring voltages and currents at grid frequencies. Reducing this intersample timing error can produce more stable and reliable voltage and current measurements. As monitoring systems are developed or programmed to monitor and/or report readings on shorter and shorter time intervals, that is, at higher sampling rates, any amount of “slippage” or intersample error tends to increase, thereby potentially compromising the accuracy of the system.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is a general object of the invention to provide a method and/or system for reducing intersample timing error.
Briefly and in accordance with the foregoing object, a system clock for a system for measuring at least one given quantity having a value which does not vary significantly from a given frequency, comprises a controller for sampling said given quantity at a rate determined by an oscillator frequency, and a programmable oscillator for generating said oscillator frequency, said programmable oscillator being programmable to produce said oscillator frequency at a frequency which is substantially identical to a high order harmonic of said given frequency of the quantity to be measured.
In accordance with another aspect of the invention, an improvement in a system clock for a system for measuring at least one given quantity having a periodic value which does not vary significantly from a given frequency, comprises a controller for sampling said given quantity at a rate determined by an oscillator frequency, and a programmable oscillator for generating said oscillator frequency, said programmable oscillator being programmable to produce said oscillator frequency at a frequency which is substantially identical to a high order harmonic of said given frequency of the quantity to be measured.
In accordance with another aspect of the invention, a method for controlling a sampling rate for measuring at least one given quantity which does not vary significantly from a given frequency, comprises providing a programmable oscillator, and programming said oscillator to oscillate at a frequency which is substantially identical to a high order harmonic of said given frequency.


REFERENCES:
patent: 4811052 (1989-03-01), Yamakawa et al.
patent: 5471176 (1995-11-01), Henson et al.
patent: 5742208 (1998-04-01), Blazo
patent: 5754437 (1998-05-01), Blazo
patent: 6028488 (2000-02-01), Landman et al.
patent: 6044332 (2000-03-01), Korsah et al.
“Powerlogic® Advanced Power Reliability Solutions,” Square D Schneider Electric, brochure, 2000, 3 pages.
“Powerlogic® Circuit Monitor —Series 2000,” , Square D Schneider Electric, brochure, 3 pages.
“Powerlogic® Power Meter,” , Square D Schneider Electric, brochure, 1998, 2 pages.
“Powerlogic® Metering & Monitoring Devices,” Square D Schneider Electric, brochure, 2000, 2 pages.
“Powerlogic® Power Monitoring and Control System,” Square D Schneider Electric, brochure, 1998, 4 pages.
“Powerlogic® Series 4000 Circuit Monitor,” Square D Schneider Electric, brochure, 2000, 3 pages.
“Powerlogic® System Architecture and Application Guide,” Data Bulletin, Square D Schneider Electric, May 2000.

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