Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Reexamination Certificate
2005-09-27
2005-09-27
Tsai, Henry W. H. (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
C712S235000
Reexamination Certificate
active
06950927
ABSTRACT:
A system and method process data elements with instruction-level parallelism. An instruction buffer holds a first instruction and a second instruction, the first instruction being associated with a first thread, and the second instruction being associated with a second thread. A dependency counter counts satisfaction of dependencies of instructions of the second thread on instructions of the first thread. An instruction control unit is coupled to the instruction buffer and the dependency counter, the instruction control unit increments and decrements the dependency counter according to dependency information included in instructions. An execution switch is coupled to the instruction control unit and the instruction buffer, and the execution switch routes instructions to instruction execution units.
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patent: 2001/0023479 (2001-09-01), Kimura et al.
Apisdorf Joel Zvi
Sandbote Sam Brandon
Grunkemeyer Joseph T.
Karasek John J.
The United States of America as represented by the Secretary of
Tsai Henry W. H.
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