Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2000-12-28
2002-07-23
Elms, Richard (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S185110
Reexamination Certificate
active
06424556
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly, to techniques for enhancing performance characteristics of a compilable read-only memory (ROM) instance.
2. Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a “design gap” between today's electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers' productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the “deep submicron” problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that various types of circuitry such as analog blocks, non-volatile memory (e.g., read-only memory or ROM), random access memories (RAMs), and other “non-logic” cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take several staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs' as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design re-use is through what are known as Intellectual Property (“IP”) components—pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system. Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory, including ROM, is a key technology driver for SOC design. It is also well known that speed and power consumption are two major factors in designing a high performance ROM core. In typical ROM architectures, a transistor is placed at the intersection of every bitline (BL) and wordline (WL) with the transistor' gate being connected to the WL. Depending on the actual ROM code to be programmed, the transistor of the bit cell is either connected to the BL (for storing a binary 0) or left open (for storing a binary 1).
It should be appreciated that as the number of binary 0's on a BL increases, its capacitance also increases because of the parasitic diffusion capacitance of the transistor's drain connected thereto. It is possible that in some instances the ROM code to be programmed may have a large number of 0's on one or more BLs, resulting in degraded performance with respect to both speed and power. First, as more 0's are programmed on a BL, that particular BL will discharge more often during access cycles because of its pre-charge condition. This, in turn, implies that the BL will consume more power for bringing it back to a pre-charge condition relative to a BL that has more 1's. Further, the same power consumption constraints also apply to the entire ROM core on a per input/output (I/O) block basis even where individual BL loading of binary 0's is relatively comparable across the,BLs of a particular I/O block.
In addition, having more 0's on a BL results in larger parasitic capacitance which leads to a slower rate of discharge. Consequently, access time characteristics of the ROM are severely degraded. Clearly, this leads to undesirable operating conditions for high performance embedded applications.
Based on the foregoing, it should be readily recognized that there has arisen an acute need for an effective yet efficient solution that increases performance characteristics of ROMs without incurring unacceptable penalties in silicon area, design complexity, or process flow required for its implementation. It would be of further advantage that the solution be adaptable for compilable ROM architectures so that increased performance may be realized in embedded applications as well.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to providing techniques for increasing performance by reducing bitline capacitance (hence increasing speed and lowering power consumption) in a compilable ROM core by manipulating the distribution of the binary contents therein. In one aspect, the present invention provides a low power technique wherein the contents of at least one I/O block of the ROM are manipulated (e.g., inverted) such that the binary 0's in that I/O block are no more than 50%. Output path circuitry associated with the I/O block is suitably manipulated in order to facilitate accurate outputting of the original data to be stored therein. Essentially, an “inverter path” portion is selectively enabled for the output path circuitry during the via fabrication step effectuated for mask-level programming of the ROM.
In another aspect, the present invention provides a technique wherein the contents of a single bitline of the ROM are inverted such that the binary 0's on that bitline are no more than 50%. Both speed and power advantages are accordingly realized in this technique. Again, the output path associated with the bitline is suitably manipulated by selectively enabling an inverter path portion for accurately outputting the original data on the bitline. Logic circuitry is included for generating appropriate control signals for selective activation of the inverter path portion in the output path.
In yet another aspect, the present invention is directed to a technique wherein row and column addresses are scrambled for achieving a desired distribution of the data map to be programmed into the ROM. Upon providing a predetermined data map, the number and distribution of binary 0's and 1's in the ROM are analyzed under normal row and column addressing. Thereafter, a select portion of the row addresses is interchanged with a select portion of the column addresses and the distribution of 0's and 1's is analyzed again under the scrambled addressing scheme. This process of scrambling addresses and comparing the resultant distributions of the binary data may take place until various possible combinations of row and column address interchanging have been verified. Subsequently, a particular addressing scheme is selected for programming the ROM with the pattern having the best possible distribution of 0's and 1's that optimizes speed and power.
In a still further aspect, the present invention is directed to a compilable ROM with enhanced performance characteristics for storing a predetermined data map. A plurality of memory locations of the ROM are organized into one or more I/O blocks having a select number of bitlines. At least a portion of the memory locations have data therein in a manipulated form (i.e., inverted). Suitable circuitry, preferably selectively activatable, is provided for accurate outputting of the original data intended for storage in the memory portion. In one exemplary embodiment, the circuitry is comprised of an inverter path portion in output path circuitry that can be enabled by appropriate placement of vias during mask-level programming of the ROM. In another exemplary embodiment, the circuitry is comprised of logic blocks for generating appropriate enable signals that select between an inverter path portion and a normal path portion in the output path circuitry.
In yet further aspect, the present invention is directed to a compilable ROM having a data map programmed with a scrambled addressing scheme wherein at least a portion of the row and column addresses is interchanged
Kablanian Adam Aleksan
Sabharwal Deepak
Danamraj & Youst P.C.
Elms Richard
Phung Anh
Virage Logic Corp.
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