Boots – shoes – and leggings
Patent
1977-06-23
1979-03-13
Thomas, James D.
Boots, shoes, and leggings
G06F 300
Patent
active
041445627
ABSTRACT:
A system and method is disclosed wherein a microprocessor having an eight-bit data bus and a sixteen-bit address bus is interconnected with a peripheral device to which a certain amount of data must be transferred at a data rate greater than is possible by utilizing the eight-bit data bus to accomplish the transfer. The system includes a microprocessor, a memory, and a peripheral device interconnected by the eight-bit data bus, the sixteen-bit address bus and a read-write conductor. The peripheral device includes an address code recognition circuit coupled to the data bus and one of the address lines, and also includes a fifteen-bit buffer connected to fifteen lines of the address bus. The address code recognition circuit generates an output which is gated with the read-write conductor to generate a clock signal which enables the data on the address bus to be loaded into the fifteen-bit buffer, from which it may be utilized by the peripheral device. During two microprocessor read cycles, two eight-bit bytes of data are loaded from the memory into the microprocessor via the data bus. Fifteen of these sixteen bits constitute data to be rapidly transferred to the peripheral device, and one bit is programmed as an enable bit to be inputted to the address code recognition circuit. During another microprocessor read cycle, another eight-bit byte including a peripheral address code is loaded from the memory into the microprocessor via the data bus. During a first portion of a microprocessor write cycle, the fifteen bits of data to be transferred to the peripheral device and the enable bit are outputted on the address bus. During a second portion of the same write cycle, the peripheral address code is out-putted on the data bus. If the enable bit is programmed to be a "1", and the peripheral address code is the one that the address code recognition circuit is set up to recognize, the code recognition circuit generates an enable signal which in turn is ANDed with a write pulse from the read-write conductor to produce a clock enable signal which enables the fifteen bits of data to be loaded into the fifteen-bit buffer. The fifteen bits of data are then available for utilization by the peripheral device.
REFERENCES:
patent: 3821715 (1974-06-01), Hoff, Jr.
patent: 3938098 (1976-02-01), Garlic
Cavender J. T.
Dugas Edward
NCR Corporation
Thomas James D.
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