Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
1999-08-09
2001-06-19
Chin, Stephen (Department: 2734)
Pulse or digital communications
Equalizers
Automatic
C375S229000, C375S230000, C375S231000, C375S263000, C375S346000
Reexamination Certificate
active
06249544
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to methods and systems for decoding received encoded signals and, more particularly, for decoding and ISI compensating multi-dimensional trellis-coded signals with a minimum of computational complexity and propagation delays in the logic circuits.
DESCRIPTION OF THE RELATED ART
In recent years, local area network (LAN) applications have become more and more prevalent as a means for providing local interconnect between personal computer systems, work stations and servers. Because of the breadth of its installed base, the 10BASE-T implementation of Ethernet remains the most pervasive if not the dominant, network technology for LANs. However, as the need to exchange information becomes more and more imperative, and as the scope and size of the information being exchanged increases, higher and higher speeds (greater bandwidth) are required from network interconnect technologies. Among the highspeed LAN technologies currently available, fast Ethernet, commonly termed 100BASE-T, has emerged as the clear technological choice. Fast Ethernet technology provides a smooth, non-disruptive evolution from the 10 megabit per second (Mbps) performance of 10BASE-T applications to the 100 Mbps performance of 100BASE-T. The growing use of 100BASE-T interconnections between servers and desktops is creating a definite need for an even higher speed network technology at the backbone and server level.
One of the more suitable solutions to this need has been proposed in the IEEE 802.3ab standard for gigabit ethernet, also termed 1000BASE-T. Gigabit ethernet is defined as able to provide 1 gigabit per second (Gbps) bandwidth in combination with the simplicity of an ethernet architecture, at a lower cost than other technologies of comparable speed. Moreover, gigabit ethernet offers a smooth, seamless upgrade path for present 10BASE-T or 100BASE-T ethernet installations.
In order to obtain the requisite gigabit performance levels, gigabit ethernet transceivers are interconnected with a multi-pair transmission channel architecture. In particular, transceivers are interconnected using four separate pairs of twisted Category-5 copper wires. Gigabit communication, in practice, involves the simultaneous, parallel transmission of information signals, with each signal conveying information at a rate of 250 megabits per second (Mb/s). Simultaneous, parallel transmission of four information signals over four twisted wire pairs poses substantial challenges to bidirectional communication transceivers, even though the data rate on any one wire pair is “only” 250 Mbps.
In particular, the gigabit ethernet standard requires that digital information being processed for transmission be symbolically represented in accordance with a five-level pulse amplitude modulation scheme (PAM-5) and encoded in accordance with an 8-state Trellis coding methodology. Coded information is then communicated over a multi-dimensional parallel transmission channel to a designated receiver, where the original information must be extracted (demodulated) from a multi-level signal. In gigabit Ethernet, it is important to note that it is the concatenation of signal samples received simultaneously on all four twisted pair lines of the channel that defines a symbol. Thus, demodulator/decoder architectures must be implemented with a degree of computational complexity that allows them to accommodate not only the “state width” of Trellis coded signals, but also the “dimensional depth” represented by the transmission channel.
Computational complexity is not the only challenge presented to modern gigabit capable communication devices. A perhaps greater challenge is that the complex computations required to process “deep” and “wide” signal representations must be performed in an almost vanishingly small period of time. For example, in gigabit applications, each of the four-dimensional signal samples, formed by the four signals received simultaneously over the four twisted wire pairs, must be efficiently decoded within a particular allocated symbol time window of about 8 nanoseconds.
Successfully accomplishing the multitude of sequential processing operations required to decode gigabit signal samples within an 8 nanosecond window requires that the switching capabilities of the integrated circuit technology from which the transceiver is constructed be pushed to almost its fundamental limits. If performed in conventional fashion, sequential signal processing operations necessary for signal decoding and demodulation would result in a propagation delay through the logic circuits that would exceed the clock period, rendering the transceiver circuit non-functional. Fundamentally, then, the challenge imposed by timing constraints must be addressed if gigabit Ethernet is to retain its viability and achieve the same reputation for accurate and robust operation enjoyed by its 10BASE-T and 100BASE-T siblings.
In addition to the challenges imposed by decoding and demodulating multilevel signal samples, transceiver systems must also be able to deal with intersymbol interference (ISI) introduced by transmission channel artifacts as well as by modulation and pulse shaping components in the transmission path of a remote transceiver system. During the demodulation and decoding process of Trellis coded information, ISI components are introduced by either means must also be considered and compensated, further expanding the computational complexity and thus, system latency of the transceiver system. Without a transceiver system capable of efficient, high-speed signal decoding as well as simultaneous ISI compensation, gigabit ethernet would likely not remain a viable concept.
SUMMARY OF THE INVENTION
The present invention is directed to a receiver and a method for decoding and ISI compensating signal samples. The receiver demodulates an analog signal transmitted by a remote transmitter over a transmission channel. The analog signal includes a first ISI component induced by a characteristic of a pulse shaping filter included in the remote transmitter and a second ISI component induced by a characteristic of the transmission channel. The receiver includes an analog front end, an equalizer block and a decision feedback sequence estimation block. The analog front end includes an analog-to-digital converter, receives and converts the analog signal to a first digital signal. The equalizer block compensates the first ISI component in the first digital signal and outputting a second digital signal. The decision feedback sequence estimation block includes an ISI compensation circuit which receives the second digital signal and compensates the second ISI component in the second digital signal.
In one aspect of the invention, the receiver includes an analog front end, incorporating an analog-to-digital converter which converts analog signal samples communicated over a multi-pair transmission channel into a digital representation. A first ISI compensation circuit is coupled to receive digital signal samples from the analog front end and outputs digital signal samples compensated for at least the first ISI component induced by the remote transmitter's partial response pulse shaping filter. A second ISI compensation circuit receives digital signal samples output by the first ISI compensation circuit and compensates those signal samples for the second ISI component induced by a characteristic of the multi-pair transmission channel.
In a particular aspect of the invention, the first ISI compensation circuit is constructed as an inverse partial response filter which approximates an inverse response characteristic to the remote transmitter's partial response pulse shaping filter so as to compensate digital signal samples for the first ISI component. During system start-up, the inverse partial response filter filters received signal samples with a characteristic feedback gain factor K. This characteristic feedback gain factor K is ramped from its initial value to zero after the occurrence of a pre-defined event or after
Abnous Arthur
Azazzi Oscar E.
Hatamian Mehdi
Kruse David
Broadcom Corporation
Chin Stephen
Christie Parker & Hale LLP
Ghayour Mohammad
LandOfFree
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