System and method for high precision clock recovery over...

Details System and method for high precision clock recovery over... System and method for high precision clock recovery over...

2005-06-28

2010-02-16

Shah, Chirag G (Department: 2477)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S503000, C375S354000, C375S371000

Reexamination Certificate

active

07664118

ABSTRACT:
An innovative system and method for achieving high precision clock recovery, i.e. reconstruction of the clock signal having the same frequency, over a packet switched network. The proposed method utilizes a minimum network delay approach, which overcomes the problems caused by delay variation of the network and filters out network jitter, such as noise jitter and other “singular” anomalies causing latency deviations. Minimum network delay is defined herein as the time delay in which a packet remains in the network under assumption that all transmission queues through which the packet passes are empty.

REFERENCES:
patent: 6363073 (2002-03-01), Nichols
patent: 6400683 (2002-06-01), Jay et al.
patent: 6643612 (2003-11-01), Lahat et al.
patent: 6721328 (2004-04-01), Nichols et al.
patent: 7106758 (2006-09-01), Belk et al.

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