System and method for high-bandwidth serial bus data transfer

Details System and method for high-bandwidth serial bus data transfer System and method for high-bandwidth serial bus data transfer

2006-03-28

2009-10-06

Yao, Kwang B (Department: 2416)

Multiplex communications

Channel assignment techniques

Details of circuit or interface for connecting user to the...

Reexamination Certificate

active

07599388

ABSTRACT:
A serial bus data transfer system employs an interface circuit which includes a first FIFO which receives data from a serial bus and a second FIFO which outputs data to the bus. A first processor interfaces with the FIFOs and a dual-banked shared memory comprising first and second memory banks, such that data is routed between the FIFOs and the memory banks via the first processor. A second processor interfaces with the dual-banked shared memory such that data can be bidirectionally exchanged between either memory bank and the second processor. The first memory bank can be accessed and clocked by the first processor while the second memory bank is simultaneously accessed and clocked by the second processor, and vice versa, such that data can be simultaneously transferred between the FIFOs and the second processor via the dual-banked shared memory.

REFERENCES:
patent: 6904475 (2005-06-01), Fairman
patent: 2003/0195645 (2003-10-01), Pillay et al.
“TSB43CA43A/TSB43CB43A/TSB43CA42 iceLynx-Micro IEEE 1394a-2000 Consumer Electronics Solution Abbreviated Data Manual”, SLLS546H, Dec. 2005, pp. 1-97.

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