Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2001-07-25
2004-05-18
Hjerpe, Richard (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C348S500000
Reexamination Certificate
active
06738056
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to display systems, and more particularly to a system and method for handling the input video stream for direct display on a liquid crystal display device (LCD).
BACKGROUND OF THE INVENTION
Liquid crystal displays (LCDs) are commonly used in devices such as portable televisions, portable computers, control displays, and cellular phones to display information to a user. LCDs act in effect as a light valve, i.e., they allow transmission of light in one state, block the transmission of light in a second state, and some include several intermediate stages for partial transmission. When used as a high resolution information display, as in one embodiment of the present application, LCDs are typically arranged in a matrix configuration with independently controlled pixels. Each individual pixel is signaled to selectively transmit or block light from a backlight (transmission mode), from a reflector (reflective mode), or from a combination of the two (transflective mode).
An LCD pixel can control the transference for different wavelengths of light. For example, an LCD can have pixels that control the amount of transmission of red, green, and blue light independently. In some LCDs, voltages are applied to different portions of a pixel to control light passing through several portions of dyed glass. In other LCDs, different colors are projected onto the pixel sequentially in time. If the voltage is also changed sequentially in time, different intensities of different colors of light result. By quickly changing the wavelength of light to which the pixel is exposed an observer will see the combination of colors rather than sequential discrete colors. Several monochrome LCDs can also result in a color display. For example, a monochrome red LCD can project its image onto a screen. If a monochrome green and monochrome blue LCD are projected in alignment with the red, the combination will be full color.
The monochrome resolution of an LCD can be defined by the number of different levels of light transmission that each pixel can perform in response to a control signal. A second level is different from a first level when the user can tell the difference between the two. An LCD with greater monochrome resolution will look clearer to the user.
LCDs are actuated pixel-by-pixel, either one at a time or several simultaneously. A voltage is applied to each pixel and the liquid crystal responds to the voltage by transmitting a corresponding amount of light. In some LCDs an increase in the actuation voltage decreases transmission, while in others it increases transmission. When multiple colors are involved for each pixel, multiple voltages are applied to the pixel at different positions or times depending upon the LCD. Each voltage controls the transmission of a particular color. For example, one pixel can be actuated to allow only blue light to be transmitted while another allows only green. A greater number of different light levels available for each color results in a much greater number of possible color combination.
Converting a complex digital signal that represents an image or video into voltages to be applied to the pixels of an LCD involves circuitry that can limit the monochrome resolution. The signals necessary to drive a single color of an LCD are both digital and analog. It is digital in that each pixel requires a separate selection signal, but it is analog in that an actual voltage is applied to the pixel to determine light transmission. A input video stream, such as a TV, video camera signal, etc., is usually generated by an external unit and comprises video data as well as a video clock. The video clock represent, for example, the timing of the respective pixel data in a input video stream. The conversion of an external input video stream into a internal video signal, which can control a display, such as an LCD, can introduce errors that reduce the monochrome resolution of the LCD or result in specific artifacts, such as shades, lines, etc. Therefore, display systems usually provide a buffer memory, also known as a video memory, which is read with an internal clock to generate the respective driver signals at a constant rate. The video buffer is written asynchronously, for example according to the external video clock.
SUMMARY OF THE INVENTION
The embodiments of the present application are directed to a system and method for providing system and method of handling a input video stream without the need of a buffer memory. Furthermore, it is desired to run a display driver based on a clock which is generated internally because such a clock is more reliable.
With improvements in technology it is possible in some applications to deliver video data fast enough to directly pass them into a display, such as a LCD or any other type of display. This mode according to the present application is called unbuffered operation. The advantage of such a system is obvious as it does not need a buffered memory and therefore can be manufactured at a lower price. In this mode the video data is accepted on the external video clock which is called the dot clock. This external dot clock is presented synchronously with their video data. The embodiments according to the present application accept that pixel as it is supplied and change their time domain from the external time domain to an internal time domain. This is necessary as the internal time domain is more reliable and needed to run certain circuitry within the chip. To avoid any data loss the internal data clock has to be higher in frequency than the external data clock. Normally, every once in a while this will cause a system clock pulse where there would be no data. This is called a gap in data. In prior art embodiments a buffer memory is used, so no effect on the handling of the data takes place. This is because everything is done in a step-by-step mode as the buffer is written and read with different signals causing a constant read out of the memory. However, with unbuffered data coming through a data gap will cause that the data preceding the data gap will dwell twice as long on a display pixel as normal for each pixel.
The present application avoids this by disconnecting the digital-to-analog converter from the column and not reconnecting it until after the next data has been received. Thus, a constant dwell time for each pixel is maintained.
A first embodiment for handling an input video stream comprises an internal clock generator generating a first clock and a synchronization unit receiving the input video stream having an associated second clock being slower than the first clock, whereby the synchronization unit samples the second clock with the first clock thereby generating a third clock synchronized with the first clock having no signal in case of a data gap. This signal can be used to determine the dwelling time for a charge being applied to a pixel which will be constant even without a buffer memory.
An enhanced embodiment further comprises a digital-to-analog-converter receiving video data from the video stream being controlled by the third clock.
Yet another enhanced embodiment further provides a digital-to-analog-converter receiving video data from the video stream generating an analog output signal and a sample-and-hold-unit receiving the analog output signal and being controlled by the third clock.
In yet another enhanced embodiment the synchronization unit further generates a fourth signal derived from the third signal which is time delayed for determination of pixel dwelling time.
In yet another embodiment the synchronization unit comprises a first flip-flop having a set and a reset input and an output, whereby the set input receives the second clock and the reset input receives the first clock. A first AND gate having two inputs and an output is provided, whereby the first input is coupled with the output of the first flip-flop and the second input receives the first clock. Furthermore, a second flip-flop having a set and a reset input and an output is provided, where
Baker & Botts L.L.P.
Brillian Corporation
Hjerpe Richard
Nguyen Kevin
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