Patent
1995-02-13
1997-08-05
Chan, Eddie P.
395451, 395 472, 395490, G06F 1214
Patent
active
056551037
ABSTRACT:
A system and method for identifying which incoming write data is valid and for insuring that stale data does not overwrite valid data within system memory within a symmetrical multiprocessor data processing system. Upon receipt of a Load Miss request from a processor, a stale bit is established and set equal to zero. A determination is then made of which other processor has ownership of the requested cache line. The requested cache line is then transferred in a cache-to-cache transfer from the second processor to the first processor. If the first processor further modifies the cache line and writes back the cache line to system memory before the original owner of the cache line writes back the stale data with an acknowledgment of the cache-to-cache transfer, the stale bit is set to one. Upon receipt from the acknowledgment from the original owner of the cache line, the stale data is dropped when it is determined that the stale bit has been set.
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Cheng Kai
So Kimming
Wang Jin Chin
Carwell Robert M.
Chan Eddie P.
Galasso Raymond M.
International Business Machines - Corporation
Kim Hong C.
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