Electrical computers and digital processing systems: processing – Instruction fetching – Of multiple instructions simultaneously
Patent
1997-11-03
1999-11-16
Pan, Daniel H.
Electrical computers and digital processing systems: processing
Instruction fetching
Of multiple instructions simultaneously
712216, 712 41, 712238, G06F 944, G06F 9445, G06F 9455
Patent
active
059875933
ABSTRACT:
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load/store unit is provided whose main purpose is to make load requests out-of-order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out-of-order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load/store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.
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Coon Brett
Miyayama Yoshiyuki
Nguyen Le Trong
Senter Cheryl D.
Wang Johannes
Pan Daniel H.
Seiko Epson Corporation
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