System and method for generating multiple clock signals

Details System and method for generating multiple clock signals System and method for generating multiple clock signals

2006-12-19

2006-12-19

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S291000, C327S156000

Reexamination Certificate

active

07151399

ABSTRACT:
A technique for generating multiple clock signals using a frequency generator for generating a common clock signal. A first digital divider and multiplier receives the common clock signal and produces a first clock signal. A second digital divider and multiplier receives the common clock signal and produces a second clock signal, the second clock signal being at a different frequency than the first clock signal. A third digital divider and multiplier receives the common clock signal and produces a third clock signal, the third clock signal being at a different frequency than the first clock signal and the second clock signal. The common clock signal can be the greatest common measure of the first, second and third clock signals divided by a multiple of two.

REFERENCES:
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patent: 5896428 (1999-04-01), Yanagiuchi
patent: 6294935 (2001-09-01), Ott
patent: 6600912 (2003-07-01), Stepp et al.
patent: 2002/0023239 (2002-02-01), Nomura et al.
patent: 2003/0229815 (2003-12-01), Fujiwara et al.
patent: 1 176 752 (2002-01-01), None
patent: 2002108490 (2002-04-01), None

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