System and method for generating a hazard-free asynchronous circ

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364488, G06F 1750

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057484872

ABSTRACT:
A flip-flop-based circuit architecture generates a hazard-free asynchronous signal given the SET and RESET sum-of-product (SOP) solutions to an asynchronous process. The flip-flop SET and RESET SOP solutions can be hazardous. Thus, general purpose synchronous optimization tools (which are indifferent to hazards) can be used to derive the optimal SOP solutions. A fixed layer built around the SOP cores eliminates all hazards in the circuit. In one embodiment, the architecture is optimized by eliminating an RS latch and delay lines in the SOP cores. The architecture of the present invention is guaranteed to admit any semi-modular race-free state graph representation of an asynchronous process that satisfies the n-shot requirement. The state graph representations can be examined to determine if alternate, solution-specific, simplified architectures can be employed that further decrease the final area by the elimination of flip-flops or the elimination of a timing delay.

REFERENCES:
patent: 4763289 (1988-08-01), Barzilai et al.
patent: 5282146 (1994-01-01), Aihara et al.
patent: 5469367 (1995-11-01), Puri et al.
patent: 5493505 (1996-02-01), Banerjee et al.
patent: 5550760 (1996-08-01), Razdan et al.
Beerel, P. and Meng, T., "Automatic Gate-Level Synthesis of Speed-Independent Circuits" IEEE, pp. 581-586, 1992.
Chu, T., "Synthesis of Self-timed VLSI Circuits from Graph--Theoretic Specifications" IEEE, pp. 220-223, 1987.
Kishinevsky, M.A. et al., "On Self-Timed Behavior Verification" ACM Intl. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Mar. 1992.
Kondratyev, A. et al., "Signal Graphs: A Model for Designing Concurrent Logic" Proceedings of the International Conference on Parallel Processing, pp. 51-54, Aug. 1988.
Kondratyev, A. et al, "On the Conditions for Gate-Level Speed-Independence of Asynchronous Circuits" ACM Intl. Worikshop on Timing Issues in the Specification and Synthesis of Digital Systems, Sep. 1993.
Lavagno, L. et al., "Synthesis of Hazard-free Asynchronous Circuits with Bounded Wire Delays", pp. 1-36, Nov. 19, 1992.
Lavagno, L. and A. Sangiovanni-Vincentelli, "Linear Programming for Optimum Hazard Elimination in Asynchronous Circuits" IEEE, pp. 275-278, 1992.
IMEC Laboratory, Assassin: An Asynchronous I/Q Interface Synthesis System, Nov. 15, 1993.
Moon, C. et al, "Synthesis of Hazard-free Asynchronous Circuits from Graphical Specifications" IEEE, pp. 322-325, 1992.
Murata T., "Petri Nets: Properties, Analysis and Applications", IEEE, pp. 541-580, Apr. 1989.
Norwick, S. and D. Dill, "Exact Two-Level Minimization of Hazard-Free Logic with Multiple-Input Changes", IEEE, pp. 626-630, 1992.
Sentovich, E. et al, "SIS: A System for Sequential Circuit Synthesis" pp. 1-45, May 4, 1992.
Varshavskiy, V. I. et al. "Models for Specification and Analysis of Process in Asynchronous Circuits" Scripta Technica, Inc., pp. 61-76, 1989.

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