Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2011-05-03
2011-05-03
Kindred, Alford W (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S036000
Reexamination Certificate
active
07937559
ABSTRACT:
A processor generation system includes the ability to describe processors with three instruction sizes. In one example implementation, instructions can be 16-, 24- and 64-bits. This enables a new range of architectures that can exploit parallelism in architectures. In particular, this enables the generation of VLIW architectures. According to another aspect, the processor generator allows a designer to add a configurable number of load/store units to the processor. In order to accommodate multiple load/store units, local memories connected to the processor can have multiple read and write ports (one for each load/store unit). This further allows the local memories to be connected in any arbitrary connection topology. Connection box hardware is automatically generated that provides an interface between the load/store units and the local memories based on the configuration.
REFERENCES:
patent: 4236206 (1980-11-01), Strecker et al.
patent: 5222225 (1993-06-01), Groves
patent: 5598546 (1997-01-01), Blomgren
patent: 5781750 (1998-07-01), Blomgren
patent: 5802556 (1998-09-01), Patel et al.
patent: 5812147 (1998-09-01), Van Hook et al.
patent: 5826071 (1998-10-01), Narayan
patent: 5896521 (1999-04-01), Shackleford et al.
patent: 5922066 (1999-07-01), Cho et al.
patent: 6023757 (2000-02-01), Nishimoto et al.
patent: 6026478 (2000-02-01), Dowling
patent: 6044450 (2000-03-01), Tsushima et al.
patent: 6058465 (2000-05-01), Nguyen
patent: 6233596 (2001-05-01), Kubota et al.
patent: 6272512 (2001-08-01), Golliver et al.
patent: 6332186 (2001-12-01), Elwood et al.
patent: 6366998 (2002-04-01), Mohamed
patent: 6477683 (2002-11-01), Killian et al.
patent: 6496922 (2002-12-01), Borrill
patent: 6549999 (2003-04-01), Kishida et al.
patent: 6704859 (2004-03-01), Jacobs et al.
patent: 6721866 (2004-04-01), Roussel et al.
patent: 6820195 (2004-11-01), Shepherd
patent: 6826679 (2004-11-01), Laurenti et al.
patent: 2001/0032305 (2001-10-01), Barry
patent: 2003/0014457 (2003-01-01), Desai
patent: 09-251477 (1997-09-01), None
patent: 10/134032 (1998-05-01), None
patent: 2000298652 (2000-10-01), None
patent: WO 00/46704 (2000-08-01), None
patent: WO 01/61576 (2001-08-01), None
patent: WO 01/73571 (2001-10-01), None
Gonzalez; “Xtensa: A Configurable and Extensible Processor”; 2000; IEEE.
Berekovic, M., et al., “A Programmable Co-Processor for MPEG-4 Video,” IEEE, p. 1021-1024, (2001).
Kondo, Y., et al., “A4 GOPS 3 Way—VLIW Image Recognition Processor Based on a Configurable Media-Processor,” IEEE Int'l Solid State Circuits Conf., 3 pages, (2001).
Vert, William Dr., “An Essay on Endian Order,” Dr. Bill's Notes on Little Endian vs. Big Endian, at website http://www.cs.umass.edu/˜verts/cs32/endian.html, Apr. 19, 1996.
Ercanli, E. et al., “A Register File and Scheduling Model for Application Specific Processor Synthesis”, p. 35-40 (Jun. 1996).
Iseli, C. et al., “Ac++ Compiler for FPGA Custom Execution Units Synthesis”, Proc. of IEEE Symp on FPGAs for Custom Computing Machines, p. 173-179 (Apr. 1995).
Fiske James Alexander Stuart
Gonzalez Ricardo E.
Parameswar Akilesh
Geib Banjamin P
Kindred Alford W
Pillsbury Winthrop Shaw & Pittman LLP
Tensilica, Inc.
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