System and method for formulating subsets of a hierarchical circ

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364490, 364491, 364488, G06F 1750

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active

055196284

ABSTRACT:
A computer-based system and method is provided for building subsets of a hierarchical circuit design. A VLSI circuit design component is stored in computer memory. The design component identifies a leaf design entity in the hierarchical circuit design. A set of placements is determined representing positions in the hierarchical circuit design where the VLSI circuit design component appears. The placements form a subset of instances of the leaf design entity. A set of links is created. The links are associated in memory with both the VLSI circuit design component and the placements, and connect various ones of the placements to one another to further denote placement of the VLSI circuit design component within the hierarchical circuit design. A subset list is appended to the VLSI circuit design component in computer memory. The subset list denotes the previously-determined subset and includes placements where the VLSI circuit design component is identified in the hierarchical circuit design. The identified placements may indicate exclusion of a particular instance of a design component from the hierarchical circuit design, or inclusion of a particular instance.

REFERENCES:
patent: 4815003 (1989-03-01), Putatunda et al.
patent: 5050091 (1991-09-01), Rubin
patent: 5175696 (1992-12-01), Hooper et al.
patent: 5247666 (1993-09-01), Buckwold
patent: 5267175 (1993-11-01), Hooper
patent: 5349659 (1994-09-01), Do et al.
patent: 5357440 (1994-10-01), Talbott et al.
Sinhai et al., "A Data Model and Architecture for VLSI/CAD Databases", Computer-Aided Design, 1989 International Con., 1989, pp. 276-279.
Foo et al., "Databases and Cell-Selection Algorithms for VLSI Cell Libraries", Computer Magazine, vol. 23, issue 2, Feb. 1990, pp. 18-30.
Chowdhurry et al., "Hierarchical Layout Synthesis of Analogue VLSI Circuits Using an Intelligent Parsing Mechanism", Proceedings of the 34th Midwest Symposium on Circuits and Systems, vol. 2, 14-17 May 1991, pp. 835-888.
N. Hedenstierna et al., "The Use Of Inverse Layout Trees For Hierarchical Design Rule Checking", Design Automation Conference, 1989, Paper 32.2, pp. 508-512.
C. K. Nandy et al., "Linear Time Geometrical Design Rule Checker Based on Quadtree Representation Of VLSI Mask Layouts", Computer-Aided Design, vol. 18, No. 7, Sep. 1986, pp. 380-388.
C. Niessen, "Hierarchical Design Methodologies And Tools For VLSI Chips", Proceedings Of the IEEE, vol. 71, No. 1, Jan. 1983, pp. 66-75.
T. Whitney, "A Hierarchical Design-Rule Checking Algorithm", LAMBDA, First Quarter 1981, pp. 40-43.

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