Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-05-22
2001-12-04
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S204000
Reexamination Certificate
active
06327604
ABSTRACT:
FIELD OF THE INVENTION
The invention generally relates to systems and methods for performing floating point computation, and more particularly to systems and methods for performing floating point computations which conform to behavior specified in IEEE Standard (“Std.”) 754. The invention provides a common representational format for numbers and other values for which diverse formats are specified in IEEE Std. 754.
BACKGROUND OF THE INVENTION
Digital electronic devices, such as digital computers, calculators, and other devices, perform arithmetic calculations on values in integer, or “fixed point,” format, in fractional, or “floating point” format, or both. IEEE Standard 754, (hereinafter “IEEE Std. 754” or “the Standard”)) published in 1985 by the Institute of Electrical and Electronic Engineers, and adopted by the American National Standards Institute (ANSI), defines several standard formats for expressing values in floating point format, and a number of aspects regarding behavior of computation in connection therewith. In accordance with IEEE Std. 754, a value (−1)
s
2
e
f in a representation in floating point format comprises a plurality of binary digits, or “bits,” having the structure
s e
msb
. . . e
lsb
f
msb
. . . f
lsb
where bit “s” is a sign bit indicating whether the entire value is positive or negative, bits “e
msb
. . . e
lsb
” comprise an exponent field represent the exponent “e” in unsigned binary biased format, and bits “f
msb
. . . f
lsb
” comprise a fraction field that represents the fractional portion “f” in unsigned binary format (“msb” represents “most significant bit” and “lsb” represents “least significant bit”). The Standard defines two general formats, namely, a “single” format which comprises thirty-two bits, and a “double” format which comprises sixty-four bits. In the single format, there is one sign bit “s,” eight bits “e
7
. . . e
0
” comprising the exponent field and twenty-three bits “f
22
. . . f
0
” comprising the fraction field. In the double format, there is one sign bit “s,” eleven bits “e
10
. . . e
0
” comprising the exponent field and fifty-two bits “f
51
. . . f
0
” comprising the fraction field.
As indicated above, the exponent field of the floating point representation “e
msb
. . . e
lsb
” represents the exponent “E” in biased format. The biased format provides a mechanism by which the sign of the exponent is implicitly indicated. In particular, the bits “e
msb
. . . e
lsb
” represent a binary encoded value “e” such that “e=E+bias.” This allows the exponent E to extend from −126 to +127, in the eight-bit “single” format, and from −1022 to +1023 in the eleven-bit “double” format, and provides for relatively easy manipulation of the exponents in multiplication and division operations, in which the exponents are added and subtracted, respectively.
IEEE Std.754 provides for several different formats with both the single and double formats which are generally based on the bit patterns of the bits “e
msb
. . . e
lsb
” comprising the exponent field and the bits f
msb
. . . f
lsb
comprising the fraction field. If a number is represented all of the bits “e
msb
. . . e
lsb
” of the exponent field are binary one's (that is, if the bits represent a binary-encoded value of “255” in the single format or “2047” in the double format) and all of the bits f
msb
. . . f
lsb
of the fraction field are binary zeros, then the value of the number is positive or negative infinity, depending on the value of the sign bit “s;” in particular, the value “v” is v=(−1)
s
∞, where “∞” represents the value “infinity.” On the other hand, If all of the bits “e
msb
. . . e
lsb
” of the exponent field are binary one's and if the bits f
msb
. . . f
lsb
of the fraction field are not all zero's, then the value that is represented is deemed “not a number,” abbreviated in the Standard by “NaN.”
If a number has an exponent field in which the bits “e
msb
. . . e
lsb
” are neither all binary ones nor all binary zeros (that is, if the bits represent a binary-encoded value between 1 and 254 in the single format or between 1 and 2046 in the double format), the number is said to be in a “normalized” format. For a number in the normalized format, the value represented by the number is v=(−1)
s
2
e-bias
(1.|ƒ
msb
. . . ƒ
lsb
) where “|” represents a concatenation operation. Effectively, in the normalized format, there is an implicit most significant digit having the value “one,” so that the twenty-three digits in the fraction field of the single format, or the fifty-two digits in the fraction field of the double format, will effectively represent a fraction having twenty-four digits or fifty-three digits of precision, respectively.
Finally, if a number has an exponent field in which the bits “e
msb
. . . e
lsb
” are all binary zeros, representing the binary-encoded value of “zero,” the number is said to be in a “de-normalized” format. For a number in the de-normalized format, the value represented by the number is v=(−1)
s
2
e-bias
(0.|ƒ
msb
. . .ƒ
lsb
). It will be appreciated that the range of values of numbers that can be expressed in the de-normalized format is disjoint from the range of values of numbers that can be expressed in the normalized format, for both the single and double formats.
A problem arises in connection with numbers in the de-normalized format. In particular, numbers in the de-normalized format are difficult to process and to produce.
SUMMARY OF THE INVENTION
The invention provides anew and improved system and method for performing floating point computations on numbers using a new representation that provides a common representational format for numbers which would, in accordance with the IEEE Std. 754, be in normalized format as well as numbers which would, in accordance with the IEEE Std. 754, be in de-normalized format. The invention further provides an arrangement for converting numbers between the new representation and the respective normalized or de-normalized format, as appropriate.
In brief summary, embodiments of the invention provide a system for performing floating point computation in connection with numbers in a base floating point representation that defines a plurality of formats, including a normalized format and a de-normalized format, using a common floating point representation that defines a unitary normalized format. The system comprises a base to common representation converter and a processor. The base to common representation converter is configured to convert the numbers in the base floating point representation to a common floating point representation, so that all numbers involved in a computation will be expressed in the unitary normalized format. The processor is configured to perform a mathematical operation of at least one predetermined type in connection with the converted numbers generated by said representation converter to generate a floating point result in the common representation. Embodiments of the invention can further comprise a common to base representation converter configured to convert numbers from the common floating point representation selectively to either the normalized or de-normalized format of the base representation. In particular embodiments of the invention, the base floating point representation corresponds to that defined by the IEEE Std. 754.
By providing a common floating point representation, the floating point numbers in the base floating point representation that are to be used during a computation can be converted to the common floating point representation, and the computation can proceed using the common representation. This will eliminate the necessity of converting numbers between normalized and de-normalized formats during the computation which may be necessary in, for example, computations involving numbers that are represented in different formats in the IEEE Std.754 representation.
REFERENCES:
patent: 5511016 (1996-04-0
Cesari and McKenna LLP
Mai Tan V.
Sun Microsystems Inc.
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