System and method for fault analysis of semiconductor integrated

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

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324 713, 250207, G01R 3100

Patent

active

057034923

ABSTRACT:
In a fault analysis of large-scale integrated (LSI) circuits, a potential distribution image of a non-defective product and another potential distribution image of a defective product are displayed alternately and continuously in time, so that it is possible to acquire in real time an image of any location within a whole surface of the LSI chip. As a result, it can be viewed as if the potential distribution image of the non-defective product and the potential distribution image of the defective product are overlapped or superimposed with over time. Accordingly, a different portion between the non-defective and defective potential distribution images can be seen distinguishably from a coincident portion between the non-defective and defective potential distribution images, so that it is possible to trace the different portion in real time.

REFERENCES:
patent: 5210487 (1993-05-01), Takahashi et al.

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