Radiant energy – Means to align or position an object relative to a source or...
Reexamination Certificate
2000-03-23
2003-05-06
Anderson, Bruce (Department: 2881)
Radiant energy
Means to align or position an object relative to a source or...
C250S492200, C250S398000, C250S310000
Reexamination Certificate
active
06559457
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to semiconductor processing and, more particularly, to a system and method for facilitating detection of defects on a wafer.
BACKGROUND OF THE INVENTION
The tendency of semiconductor devices such as integrated circuits (IC) and large scale integrated circuits (LSIC) toward minuteness has rapidly progressed, and higher accuracy has been required of apparatuses for manufacturing such semiconductor devices. In particular, such requirements are demanded from exposure devices in which a circuit pattern of a mask or a reticle is superposedly transferred onto a circuit pattern formed on a semiconductor wafer. It is desired that the circuit pattern of the mask and the circuit pattern of the wafer be superposed one upon the other with accuracies of, for example, less than 0.1 &mgr;m.
In order to remain competitive, semiconductor manufacturers continually strive to reduce costs associated with manufacturing semiconductor chips while at the same time improving yield in the manufacturing process. However, wafer defects typically result in decreased yield and, in turn, provide associated increases in the manufacturing cost. Some defects exist, for example, on blank wafers as purchased. Other defects might be caused during manufacturing, such as by one of the process tools into which the wafer is placed.
Various methodologies exist for detecting and analyzing defects on wafer surfaces. One type of detector is a laser surface particle detector (LSPD) which measures amount, location, and size of particles on the wafer surface. A scanning electron microscope (SEM) equipped with an energy dispersive x-ray spectroscopy (EDS) system often is used to generate chemical information about the wafer surface layer. Because the LSPD by itself may not be sufficient for identifying a source of the particles, the LSPD system may be combined with the SEM/EDS system to locate particles on the wafer surface and to analyze the particles, respectively. The combined system is known as a particle analysis system (PAS), which is commonly used throughout the semiconductor industry. A coordinate system employed by the SEM usually is not the same as that used by the LSPD. Consequently, appropriate coordinate transforms are utilized to convert position data between the two coordinate systems.
In order to improve yield and reduce manufacturing costs, it is desirable to minimize defects caused by processing tools. Accordingly, various inspection tools, such as those commercially available from KLA-Tencor and Inspex, have been developed to map and record wafer surface defects. One particular approach to obtain information about individual specific processing tools is to employ blank test wafers during test procedures. For example, it is known to utilize a blank wafer that is marked with at least two fiducial marks. The number and position of any initial defects on the blank wafer are determined relative to the fiducial marks and the relative coordinates of the initial defects and fiducial marks are recorded. The wafer is then placed in a selected process tool and processed accordingly. The processed wafer is then analyzed again, such as in a LSPD, to determine the number and position of additional defects caused by the process tool and the coordinates of each additional defect is recorded. An analysis tool may then be employed to analyze each of the additional defects by mapping the coordinates of the defects and fiducial marks from the LSPD to the coordinate frame of the analysis tool using an appropriate coordinate transform. However, the fiducial marks occupy valuable wafer real estate, which is an ever increasingly desired commodity in light of market demands for increased device density.
There is a strong need in the art for a system and/or methodology which mitigates at least some of the short comings of convention defect detection systems and/or methods.
SUMMARY OF THE INVENTION
The present invention relates to a system and method for facilitating detection of wafer defects.
A wafer is supported by the surface of a stage, support or platform (hereinafter referred to by “stage”). The surface of the stage has a coordinate system associated therewith, and preferably surface markings coincident with the coordinate system. Preferably, the wafer has at least one edge mark to facilitate determining wafer orientation via the stage coordinate system. The stage markings are employed to facilitate determining position of a wafer placed on the stage, and to facilitate mapping to points of interest (e.g., defect locations) on the wafer. For example, when a wafer is placed on the stage, the stage markings are employed to facilitate determining the size of the wafer, the position of the wafer relative to the stage and the location of various sections of the wafer relative to the stage. A wafer surface defect procedure may be employed on the wafer, and the location of wafer surface defects determined and those locations stored in a memory. If the wafer is removed from the stage and later placed back on the stage, the present invention can readily determine the location of the defects by the mappings stored in the memory. The wafer does not have to be placed in the same location and/or orientation as it was earlier placed. The stage coordinate system provides for determining the location and/or orientation of the wafer, and for relocating wafer surface defects based on the earlier mappings thereof.
The present invention mitigates the need for employing fiducial marks on the surface of the wafer as compared to conventional systems. As a result, the present invention facilitates efficient utilization of valuable wafer surface real estate.
One aspect of the present invention relates to a system for facilitating detection of defects on a wafer. A stage receives the wafer, and the stage has a plurality of reference markings which form a reference coordinate system. A scanning system associated with the stage locates defect(s) of the wafer. The defects are mapped relative to the reference coordinate system of the stage.
Another aspect of the present invention relates to a system for facilitating detection of defects on a wafer. The system includes reference means for receiving the wafer and providing a reference coordinate system; and means for mapping a defect of the wafer relative to the reference coordinate system.
Another aspect of the present invention relates to a method for facilitating detection of defects on a wafer located on a stage. Reference markings on the stage are located, and defects of the wafer relative to the reference markings of the stage are mapped.
Still another aspect of the present invention relates to a system for mapping a wafer. A support system supports the wafer—the support system has a reference system associated therewith. A locating system determines via the reference system a position and orientation of the wafer relative to the support system. A mapping system maps the position and orientation of the wafer based on information from the locating system. The mapping system also maps at least one point of interest on the wafer surface. A storing system stores the mapping information.
Another aspect of the present invention relates to a system for mapping a wafer. A stage supports the wafer—the stage includes a plurality of reference marks. A first system determines location and orientation of the wafer relative to the stage via the reference marks. A second system detects points of interest on the wafer. A third system determines the location of the points of interest relative to the wafer via the reference marks. A fourth system maps the location of the points of interest relative to the wafer. It is to be appreciated that this aspect of the present invention is not limited to four sub-systems, and that any number (N) of sub-systems may be employed to carry out one or all of the functions of the aforementioned four sub-systems.
Yet another aspect of the present invention relates to a wafer stage. The stage includes a top surface for supporting a w
Phan Khoi A.
Rangarajan Bharath
Singh Bhanwar
Amin & Turocy LLP
Anderson Bruce
Wells Nikita
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