System and method for executing and completing store instruction

Details System and method for executing and completing store instruction System and method for executing and completing store instruction

1999-07-29

2000-10-17

Coleman, Eric

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

712 41, G06F 9312

Patent

active

061346462

ABSTRACT:
In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit. The store instruction is completed when all older instructions have completed and when all instructions in the instruction group have finished.

REFERENCES:
patent: 5467473 (1995-11-01), Kahle
patent: 5488729 (1996-01-01), Vegesna
patent: 5659782 (1997-08-01), Senter
patent: 5903740 (1999-05-01), Walker

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