Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Quality evaluation
Reexamination Certificate
2007-03-20
2007-03-20
Tsai, Carol S. W. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Quality evaluation
C702S035000, C702S082000, C702S083000, C702S084000, C700S109000, C700S110000, C700S121000
Reexamination Certificate
active
10274439
ABSTRACT:
A system and method for determining the early life reliability of an electronic component, including classifying the electronic component based on an initial determination of a number of fatal defects, and estimating a probability of latent defects present in the electronic component based on that classification with the aim of optimizing test costs and product quality.
REFERENCES:
patent: 4335459 (1982-06-01), Miller
patent: 5250895 (1993-10-01), Harigai
patent: 5377148 (1994-12-01), Rajsuman
patent: 5539652 (1996-07-01), Tegethoff
patent: 5822218 (1998-10-01), Moosa et al.
patent: 5946213 (1999-08-01), Steffan et al.
patent: 5991699 (1999-11-01), Kulkarni et al.
patent: 6047083 (2000-04-01), Mizuno
patent: 6132108 (2000-10-01), Kashiwamura et al.
patent: 6223097 (2001-04-01), Hashimoto et al.
patent: 6242270 (2001-06-01), Nagaswami et al.
patent: 6324481 (2001-11-01), Atchison et al.
patent: 6393602 (2002-05-01), Atchison et al.
patent: 6423558 (2002-07-01), Maeda et al.
patent: 6496788 (2002-12-01), Kikuchi
patent: 6539106 (2003-03-01), Gallarda et al.
patent: 6741940 (2004-05-01), Mugibayashi et al.
patent: 6789032 (2004-09-01), Barbour et al.
patent: 2001/0042705 (2001-11-01), Nakagaki et al.
patent: 2002/0053065 (2002-05-01), Mitsutake et al.
patent: 2002/0142522 (2002-10-01), Pnueli et al.
patent: 2003/0003606 (2003-01-01), Farnworth et al.
patent: 2003/0178692 (2003-09-01), Farnworth et al.
patent: 10036118 (2002-02-01), None
patent: 0660385 (1995-06-01), None
patent: WO-0005759 (2000-02-01), None
V. Riviere, A. Touboul, S. Ben Amor, G. Gregoris, J.L. Stevenson, P.S. Yeung, Evidence of a Correlation Between Process Yields and Reliability Data for a Rad-Hard Sol Technology, Int. Conference on Microelectronic Test Structures, Mar. 1995, p. 221-224, vol. 8.
Barnett, Thomas S., Singh, Adit D., Nelson, Victor P.; “Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model”; 2001 IEEE; pp. 326-332.
Barnett, Thomas S., Singh, Adit D., Nelson, Victor P.; “Yield-Reliability Modeling for Fault Tolerant Integrated Circuits”; Proceedings of the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'01); 2001 IEEE; 10 pgs.
Huston, Hance H., Clarke, C. Patrick; “Reliability Defect Detection and Screening During Processing—Theory and Implementation”; 1992 IEEE/IRPS; pp. 268-275.
Kuper, Fred, Pol, Jacob van der, Johnson, Tim, Wijburg, Rutger, Koster, Willem, Johnston, Dave; “Relation Between Yield and Reliability of Integrated Circuits: Experimental Results and Application to Continuous Early Failure Rate Reduction Programs”; 1996 IEEE; pp. 17-21.
Lakin, David R. II, Singh, Adit D.; “Exploiting Defect Clustering to Screen Bare Die for Infant Morality Failures: An Experimental Study”; ITC International Test Conference, Paper 2.1; 1999 IEEE; pp. 23-30.
McCluskey, E.J., Buelow, Fred; “IC Quality and Test Transparency”; IEEE Transactions on Industrial Electronics; May 1989; vol. 36, No. 2; 1989 IEEE; pp. 197-202.
Nigh, Phil, Needham, Wayne, Butler, Ken, Maxwell, Peter, Aitken, Rob; “An Experimental Study Comparing the Relative Effectiveness of Functional, Scan, IDDq and Delay-fault Testing”; 1997 IEEE; pp. 459-464.
Pol, Jacob A. van der, Ooms, Eric R., Hof, Toon van 't, Kuper, Fred G.; “Impact of Screening of Latent Defects at Electrical Test on the Yield-Reliability Relation and Application to Burn-in Elimination”; IEEE 98CH36173, 36thAnnual International Reliability Physics Symposium, Reno, Nevada, 1998; 1998 IEEE; pp. 370-377.
Riordan, Walter Carl, Miller, Russell, Sherman, John M., Hicks, Jeffrey; “Microprocessor Reliability Performance as a Function of Die Location for a 0.25u, Five Layer Metal CMOS Logic Process”; IEEE 99CH36296, 37thAnnual International Reliability Physics Symposium, San Diego, California, 1999; 1999 IEEE; pp. 1-11.
Singh, A.D., Krishna, C.M.; “Chip Test Optimization Using Defect Clustering Information”; 1992 IEEE; pp. 366-373.
Singh, A.D., Krishna, C.M.; “On Optimizing VLSI Testing for Product Quality Using Die-Yield Protection”; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; May 1993; vol. 12, No. 5; 1993 IEEE; pp. 695-709.
Singh, A.D., Krishna, C.M.; “On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction”; International Test Conference 1991, Paper 8.3; 1991 IEEE; pp. 228-237.
Singh, A.D., Krishna, C.M.; “On the Effect of Defect Clustering on Test Transparency and IC Test Opitimization”; IEEE Transactions on Computers; Jun. 1996; vol. 45, No. 6; 1996 IEEE; pp. 753-757.
Singh, Adit D., Lakin, David R. II, Sinha, Gaurav, Nigh, Phil; “Binning for IC Quality: Experimental Studies on the SEMATECH Data”; 7 pgs.
Singh, Adit D., Nigh, Phil, Krishna, C.M.; “Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study”; International Test Conference, Paper 15.2; 1997 IEEE; pp. 362-369.
Stapper, C.H.; “Correlation Analysis of Particle Clusters on Integrated Circuit Wafers”; IBM J. Res. Develop.; Nov. 1987; vol. 31, No. 6; pp. 641-650.
Stapper, C. H., McLaren, A.N., Dreckmann, M.; “Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product”; IBM J. Res. Develop.; May 1980; vol. 24, No. 3; pp. 398-409.
Seth, Sharad C. & Agrawal, Vishwani D.; “Characterizing the LSI Yield Equation from Wafer Test Data”; IEEE Transactions on Computer-Aided Design; Apr. 1984; pp. 123-126; vol. Cad-3, No. 2; 1984 IEEE.
Williams, T.W. & Brown, N.C.; “Defect Level as a Function of Fault Coverage”; IEEE Transactions on Computers; Dec. 1981; pp. 987-988; vol. C-30, No. 12; 1981 IEEE.
Koren, Israel & Stapper, Charles H.; “Yield Models for Defect-Tolerant VLSI Circuits: A Review”; pp. 1-21 , date unknown.
Stapper, Charles H., Armstrong, Frederick M. and Saji, Kiyotaka; “Integrated Circuit Yield Statistics”; Proceedings of the IEEE; Apr. 1983; pp. 453-470; vol. 71, No. 4; 1983 IEEE.
V. Riviere, A. Touboul, S. Ben Amor, G. Gregoris, J.L. Stevenson, P.S. Yeung, Evidence of a Correlational Between Process Yields and Reliability Data for a Rad-Hard Soi Technology, Int. Conference on Microelectronic Test Structures, Mar. 1995, p. 221-224, vol. 8.
Barnett Thomas S.
Singh Adit D.
Auburn University
Haverstock & Owens LLP
Tsai Carol S. W.
LandOfFree
System and method for estimating reliability of components... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for estimating reliability of components..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for estimating reliability of components... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3785011