Electricity: electrical systems and devices – Safety and protection of systems and devices – With specific voltage responsive fault sensor
Reexamination Certificate
2006-06-13
2006-06-13
Sircus, Brian (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
With specific voltage responsive fault sensor
C361S056000, C361S111000
Reexamination Certificate
active
07061737
ABSTRACT:
An eletrostatic discharge (ESD) protection circuit and method for operating same are disclosed. The protection circuit for each pad of integrated circuits include a diode string connected to a first pad at its anode end having a total forward voltage drop more than, or equal to, a first supply voltage and with its cathode end passing the ESD charge, a current dissipation module with at least one N-type MOSFET for passing the ESD charge from diode string to a first common node connectable to a second supply voltage, a first diode with its anode end connected to first common node and its cathode node connected to the first pad, and a control module for controlling the current dissipation module for dissipating the ESD charge through the first common node when it causes a voltage on the first pad to surpass the total forward voltage drop of the diode string.
REFERENCES:
patent: 5413969 (1995-05-01), Huang
patent: 5946573 (1999-08-01), Hsu
patent: 6096609 (2000-08-01), Kim et al.
patent: 6469560 (2002-10-01), Chang et al.
patent: 6479870 (2002-11-01), Chen et al.
patent: 6690561 (2004-02-01), Hung et al.
patent: 6747861 (2004-06-01), Ker et al.
patent: 6765771 (2004-07-01), Ker et al.
Ker, Ming-Dou et al., “Capacitor-Couple ESD Protection Circuit for Deep-Submicron Low-Voltage CMOS ASIC”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, No. 3, (Sept. 1996), pp. 307-321.
Ker, Ming-Dou et al., “Complementary-SCR ESD Protection Circuit with Interdigitated Finger-Type Layout for Input Pads of Submicron CMOS IC's”, IEEE Transactions on Electron Devices, vol. 42, No. 7, (Jul. 1995), pp. 1297-1304.
Wu et al., A New On-Chip ESD Protection Circuit with Dual Parasitic SCR Structures for CMOS VLSI, IEEE Journal of Solid-State Circuits, vol. 27, No. 3, (Mar. 1992), pp. 274-280.
Duane Morris LLP
Patel Dharti H.
Sircus Brian
Taiwan Semiconductor Manufacturing Co. Ltd.
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