System and method for equalizing high-speed data transmission

Details System and method for equalizing high-speed data transmission System and method for equalizing high-speed data transmission

2006-06-20

2006-06-20

Vo, Don N. (Department: 2631)

Pulse or digital communications

Equalizers

Reexamination Certificate

active

07065135

ABSTRACT:
According to one embodiment of the present invention, a method for equalizing a signal includes introducing a delay into an incoming data signal to generate a first delayed signal of a first format. A plurality of drivers operable to receive the incoming signal and the first delayed signal are identified. Each of the plurality of drivers have an associated drive strength. A first driver is selected from the plurality of drivers to receive the incoming signal. The selection is based at least in part on a comparison of the drive strength associated with the first driver to a maximum output current of the first driver. A second driver is selected from the plurality of drivers to receive the first delayed signal. The selection is based at least in part on a comparison of the drive strength associated with the second driver to a maximum output current of the second driver. The incoming signal is directed to the first driver, and the first delayed signal is directed to the second driver.

REFERENCES:
patent: 6680681 (2004-01-01), Hsu et al.
patent: 2004/0008059 (2004-01-01), Chen et al.
patent: 2004/0022311 (2004-02-01), Zerbe et al.
patent: 2005/0111585 (2005-05-01), Stojanovic et al.
patent: 2005/0149659 (2005-07-01), Horowitz et al.
Zerbe et al., “Equalization and Clock Recovery for a 2.5-10Gb/s 2-PAM/4-PAM Backplane Transceiver Cell,” 2003 IEEE International Solid-State Circuits Conference, 10 pages, 2003.

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