System and method for equalizing data buffer storage and fetch r

Details System and method for equalizing data buffer storage and fetch r System and method for equalizing data buffer storage and fetch r

1997-06-27

1999-06-29

Kizou, Hassan

Electrical pulse counters, pulse dividers, or shift registers: c

Counting or dividing in incremental steps

Beam type tube

395882, 395558, 377 47, G06F 300

Patent

active

059180730

ABSTRACT:
A system and method are presented for equalizing data buffer storage and fetch rates of peripheral devices. A computer system of the present invention includes a central processing unit (CPU), first and second peripheral devices, and a data buffer. The first peripheral device stores data within the data buffer, and the second peripheral device fetches data from the data buffer. A fraction of the data buffer contains unread data (i.e. data stored within the data buffer by the first peripheral device and not yet fetched by the second peripheral device). The first peripheral device includes a reload register, the contents of which determines the rate at which the first peripheral device stores data within the data buffer. The CPU produces a reload value, which is stored within the reload register, such that the rate at which the first peripheral device stores the data within the data buffer is made substantially equal to the rate at which the second peripheral device fetches the data from the data buffer. The data buffer is preferably operated a first-in-first-out manner, and includes a write pointer and a read pointer. The CPU preferably produces the reload value such that approximately half the memory locations within the data buffer contain unread data at any given time.

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