Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing
Reexamination Certificate
2006-05-16
2006-05-16
Rodriguez, Paul L. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Timing
C713S500000, C713S502000, C716S030000
Reexamination Certificate
active
07047175
ABSTRACT:
A method and system for reducing the time required for execution of the dynamic timing simulation for a logic simulator. For a logic circuit simulator having a compilation phase and a runtime phase, a delay assessment is performed during the compilation phase in order to identify storage elements that are exempt from possible timing violations at runtime. The runtime timing checks are removed from the exempt storage elements, thereby reducing the runtime calculation effort. Additionally, combinational portions of the circuit that drive the exempt storage elements are examined for element delays that can be effectively eliminated (e.g., zero delayed) from the runtime calculations, thereby providing a further reduction in the computational overhead via the use of cycle based simulation for these.
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Gopalan Badri P.
Jain Manish
Bever Hoffman & Harms LLP
Harms Jeanette S.
Rodriguez Paul L.
Stevens Tom
Synopsys Inc.
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