System and method for enhancing erase performance in a CMOS...

Details System and method for enhancing erase performance in a CMOS... System and method for enhancing erase performance in a CMOS...

2006-12-21

2008-12-30

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220

Reexamination Certificate

active

07471572

ABSTRACT:
A system and method are disclosed for enhancing the performance of erase operations in CMOS compatible EEPROM memory cells. An EEPROM memory cell is described in which the erase voltage and the coupling ratio of the EEPROM memory cell are simultaneously decreased while maintaining the erase performance (e.g., erase speed) of the EEPROM memory cell. Significant improvement in the endurance of CMOS compatible EEPROM devices is obtained due to the enhanced erase performance of the EEPROM memory cells of the present invention.

REFERENCES:
patent: 6020231 (2000-02-01), Wang et al.
patent: 6191980 (2001-02-01), Kelley et al.
patent: 6897727 (2005-05-01), Mallinson
Kee-Yeol Na et al., “High-Performance Single Polysilicon EEPROM With Stacked MIM Capacitor,” IEEE Electron Device Letters, vol. 27, No. 4, Apr. 2006, pp. 294-296.

Affiliated with

Also associated with

Rating

System and method for enhancing erase performance in a CMOS... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for enhancing erase performance in a CMOS..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for enhancing erase performance in a CMOS... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4020388