Demodulators – Phase shift keying or quadrature amplitude demodulator
Reexamination Certificate
2001-07-27
2003-04-01
Pascal, Robert (Department: 2817)
Demodulators
Phase shift keying or quadrature amplitude demodulator
C708S627000
Reexamination Certificate
active
06542028
ABSTRACT:
BACKGROUND SECTION
1. Technical Field
This invention relates generally to electronic communication systems and more particularly to efficient demodulation and filtering of a received signal.
2. Description of the Background Art
Modem receivers typically receive a real passband signal from the transmission medium, since any real transmission medium can only carry real signals. Transmitted data are typically encoded as complex symbols, so a receiver needs to decode complex symbols to recover the data. Receivers typically convert the received real passband signal into a complex baseband signal prior to decoding.
Techniques for converting a received real passband signal into a complex baseband signal include a Hilbert filter-demodulation technique and a demodulation-low pass filter technique. Most digital filtering techniques include multiplications of input samples by predetermined filter coefficients. Most demodulation techniques include multiplications to remove the carrier signal. Physical general-purpose multipliers are typically the most costly components in electronic systems, both in terms of financial costs and efficiency.
SUMMARY
A system and method are disclosed to implement efficient demodulation and filtering of a received signal. The system for demodulation and low pass filtering comprises three add-shift-negate modules configured to receive a real sample and to produce an output equal to the real sample multiplied by a coefficient, and three accumulators, where each accumulator is configured to accumulate the outputs of one of the three add-shift-negate modules. The system also includes a multiplexer that selectively outputs the contents of the accumulators. The contents of the accumulators represent complex recovered samples. The multiplexer preferably outputs three complex recovered samples per symbol at a frame rate of 2 million symbols per second.
The system of the invention is not implemented with physical multipliers. Each shift-add-negate device multiplies a real sample by a coefficient using only shifts, addition, and negation. Each coefficient represents a value of a demodulating signal multiplied by one of a set of low pass filter coefficients. In the preferred embodiment, the set of low pass filter coefficients is 1, 3, 4, 4, 4, 3, 1. The demodulating signal has values of 1, 0, and −1. Thus, in the preferred embodiment, each shift-add-negate module either ignores the real sample or effectively multiplies the real sample by ±1, ±3, or ±4. The operation of each shift-add-negate module is controlled by the state of a state machine.
REFERENCES:
patent: 5287299 (1994-02-01), Lin
Alelyunas Carl
DesJardins Philip
Norrell Andrew L.
2Wire, Inc.
Carr & Ferrell LLP
Glenn Kimberly E
Pascal Robert
Schepler Wendi R.
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