System and method for dynamically reconfigurable computing using

Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

712229, G06F 1500

Patent

active

060584696

ABSTRACT:
A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an Instruction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA). The IFU directs reconfiguration operations, instruction fetch and decode operations, memory access operations, and issues control signals to the DOU and the AOU to facilitate instruction execution. The DOU performs data computations, and the AOU performs address computations. Each T-machine is a data transfer device having a common interface and control unit, one or more interconnect I/O units, and a second local time-base unit. The GPIM is a scalable interconnect network that facilitates parallel communication between T-machines. The set of T-machines and the GPIM facilitate parallel communication between S-machines.

REFERENCES:
patent: 4037094 (1977-07-01), Vandierendonck
patent: 4250545 (1981-02-01), Blahut et al.
patent: 4811214 (1989-03-01), Nosenchuck et al.
patent: 5036473 (1991-07-01), Butts et al.
patent: 5042004 (1991-08-01), Agrawal et al.
patent: 5068823 (1991-11-01), Robinson
patent: 5109353 (1992-04-01), Sample et al.
patent: 5280474 (1994-01-01), Nickolls et al.
patent: 5361373 (1994-11-01), Gilson
patent: 5386562 (1995-01-01), Jain et al.
patent: 5430734 (1995-07-01), Gilson
patent: 5452101 (1995-09-01), Keith
patent: 5457408 (1995-10-01), Leung
patent: 5465375 (1995-11-01), Thepaut et al.
patent: 5466117 (1995-11-01), Resler et al.
patent: 5475624 (1995-12-01), West
patent: 5475856 (1995-12-01), Kogge
patent: 5497498 (1996-03-01), Taylor
patent: 5511173 (1996-04-01), Yamaura et al.
patent: 5522083 (1996-05-01), Gove et al.
patent: 5524243 (1996-06-01), Gheorghiu
patent: 5535342 (1996-07-01), Taylor
patent: 5535406 (1996-07-01), Kolchinsky
patent: 5539888 (1996-07-01), Byers et al.
patent: 5539893 (1996-07-01), Thompson et al.
patent: 5542067 (1996-07-01), Chappell et al.
patent: 5546347 (1996-08-01), Ko et al.
patent: 5546545 (1996-08-01), Rich
patent: 5546562 (1996-08-01), Patel
patent: 5548771 (1996-08-01), Davis et al.
patent: 5548775 (1996-08-01), Hershey
patent: 5550845 (1996-08-01), Traub
patent: 5550989 (1996-08-01), Santos
patent: 5551013 (1996-08-01), Beausoleil et al.
patent: 5557734 (1996-09-01), Wilson
patent: 5600845 (1997-02-01), Gilson
Wirthlin et al. "A Dynamic Instruction Set", Apr. 1995.
Alfke, Peter, and New, Bernie, Quadrature Phase Decoder, XILINX Application Note, XAPP 012.001, pp. 8-173-8-174.
Athanas, Peter, et al., "Processor Reconfiguration Through Instruction-Set Metamorphosis," IEEE, Mar. 1993, pp. 11-18.
Athanas, Peter, "The Hokie Instant RISC Microprocessor," Electrical Engineering, VISC Internet Home Page, 1996.
Baker, Stan, "Quo vadis, EDA?", Electronic Engineering Times, Jun. 26, 1995, Issue 854, Section Design, p. 83.
Brown, Chappell, "FPGAS Address DSP Tasks," CMP Publications via Fulfillment by Individual, Inc., Electronic Engineering Times, Jul. 30, 1996, p. 33.
Casselman, Steven, "Virtual Computing and The Virtual Computer," IEEE, pp. 43-48, 1993.
Chapman, Ken, "Dynamic Microcontroller Using XC4000 FPGAs," Application Note, XILINX, Inc., Dec. 1994.
Dahl, Matthew, et al., "Emulation of the Sparcle Microprocessor with the MIT Virtual Wires Emulation System," IEEE, 1994, pp. 14-22.
Depreitere, J., et al., "A Hybrid Optoelectronic 3-D Field Programmable Gate Array Demonstrator," University of Ghent, Department of Electronics and Information Systems, Belgium.
Forrest, John, "Software Acceleration Architectures," Software Acceleration Internet Home Page, Sep. 1995.
Galloway, David, "The Transmogrifier C Hardware Description Language and Compiler for FPGAs," Department of Electrical Computer Engineering, University of Toronto, date unknown.
Hadley, James D., et al., "Design Methodologies for Partially Reconfigured Systems," Dept. of Electrical and Computer Eng., Brigham Young University, pp. 1-7.
Jones, Chris, et al., "Issues in Wireless Video Coding using Run-time-reconfigurable FPGAs," Electrical Engineering Department, University of California, Los Angeles, pp. 1-5.
Lemoine, Eric, et al., "Run Time Reconfiguration of FPGA for Scanning Genomic DataBases," LIRMM UMR 9928 CNRS/Montpellier II, France.
New, Bernie, "Estimating the Performance of XC4000E Adders and Counters," XILINX Application Note, XAPP 018, Version 2.0, pp. 1-4, Jul. 4, 1996.
Razdan, Rahul, "PRISC: Programmable Reduced Instruction Set Computers," Doctoral Thesis, Center for Research in Computing Technology, Division of Applied Sciences, Harvard University, Technical Report TR-14-94, May 1994.
Razdan, Rahul, et al., "A High-Performance Microarchitecture with Hardware-Programmable Functional Units," MICRO-27, Harvard University, Nov. 1994, pp. 1-9.
Riley, David D., et al., "Design and Evaluation of a Synchronous Triangular Interconnection Scheme for Interprocessor Communications," IEEE Transactions On Computers, vol. C-31, No. 2, Feb. 1982, pp. 110-118.
Slager, Jim, "Advanced Features Squeeze onto Processor Chip," Computer Design, Oct. 1983, pp. 189-193.
Weiss, Ray, "Viva la revolucion!" Computer Design, Sep. 1995, p. 109.
Wirble, Loring, "Dolphin's KSR buy hikes SCI outlook," Electronic Engineering Times, Nov. 13, 1995, pp. 37, 42.
Wirthlin, Michael J., et al., "A Dynamic Instruction Set Computer," Dept. of Electrical and Computer Eng., Brigham Young University.
Wirthlin, Michael J., et al., "The Nano Processor: a Low Resource Reconfigurable Processor," IEEE, 1994, pp. 23-30.
GO Giga Operations Corporation Internet Page on Intellectual Property, Oct. 1, 1995.
GO Giga Operations Corporation Release 6 Data Sheet on X213EMOD.TM., Apr. 1, 1996.
GO Giga Operations Coporation Release 2.0 Data Sheet on G900 RIC.TM., Jun. 12, 1996.
Go Giga Operations Corporation Release 3.12 for NT on RC-NTDEV-SW.TM..
Go Giga Operations Corproation FCCM 1995 & FCCM 1996 Follow Up.
ATLightSpeed.TM. promotional literature featuring 3D Scanline Texture Mapping Algorithm.
Abstract from "Video Processing Module Using A Second Programmable Logic Device Which Reconfigures A First Programmable Logic Device For Data Transformation," Assignee: Giga Operations Corporation.
XCELL: The Quarterly Journal For Xilinx Programmable Logic Users, Issue 16, First Quarter, 1995, pp. 23-29.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

System and method for dynamically reconfigurable computing using does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for dynamically reconfigurable computing using, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for dynamically reconfigurable computing using will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1602478

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.