System and method for disabling or re-enabling PCI-compliant dev

Details System and method for disabling or re-enabling PCI-compliant dev System and method for disabling or re-enabling PCI-compliant dev

1995-06-07

1997-11-25

Lee, Thomas C.

395500, 395726, 395828, 395856, G06F 1300

Patent

active

056922191

ABSTRACT:
A system and method for disabling and re-enabling PCI-compliant devices in a computer system is disclosed. The system includes a CPU, a host bus coupled to the CPU, a PCI/Host bridge coupled to the host bus, one or more PCI-compliant devices, a PCI bus coupling the PCI/Host bridge and the PCI-compliant devices, and a device, typically in the form of a digital gate, for selectively disabling or re-enabling one or more of the PCI-compliant devices. The disclosed method operates in connection with a computer system having a CPU, a PCI/Host bridge coupled to the CPU and capable of sending an IDSEL signal to the IDSEL input pin of a target PCI-compliant device when attempting a read or write operation on the target PCI-compliant device, and one or more system I/O registers having a CONFIG ENABLE bit that reflects a user's request to disable or re-enable a PCI-compliant device. The method intercepts the IDSEL signal before it reaches the IDSEL input pin of the target PCI-compliant device, provides the intercepted IDSEL signal to the input of a digital gate such as an AND gate, provides a signal corresponding to the CONFIG ENABLE bit to the input of the same digital gate, and delivers the resulting output signal from the digital gate to the IDSEL input pin of the target PCI-compliant device.

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