System and method for dicing semiconductor components

Adhesive bonding and miscellaneous chemical manufacture – Differential fluid etching apparatus – With microwave gas energizing means

Reexamination Certificate

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Details

C156S583200, C438S464000, C438S976000

Reexamination Certificate

active

06319354

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally semiconductor manufacture and particularly to a system and method for icing semiconductor components, such as bare dice and chip scale packages.
BACKGROUND OF THE INVENTION
Semiconductor components are typically manufactured using wafer level fabrication processes. Semiconductor dice, for example, are fabricated by subjecting silicon wafers to well known processes. Following the fabrication process, the dice must be separated into individual units. The separation process is sometimes referred to as “dicing”. Dicing is typically accomplished by cutting the wafer with a saw blade, an etchant, a liquid jet stream, or a laser beam.
With a conventional dicing process, the wafer can be mounted to a support member known as a “film frame”. The film frame includes a frame, and an elastomeric adhesive film stretched across the frame. The adhesive film secures the wafer to the frame, and maintains the dice in a stationary position for dicing.
Semiconductor dice can also be packaged using wafer level processes. For example, one type of package, known as a chip scale package, can be fabricated while the dice are still contained on the wafer. U.S. Pat. Nos. 5,685,885 and 5,682,061 to Khandros et al. disclose representative wafer level fabrication processes for chip scale packages. Following the packaging process, the wafers are diced to separate the chip scale packages into individual units.
With either bare dice or chip scale packages, the separated components can subsequently be transferred to a carrier adapted to hold multiple components. The carriers are used to transport the components for further processing, such as testing, and for assembling the components to circuit boards and electronic devices.
One type of carrier used widely in the industry, is manufactured by Vichem Corporation, of Sunnyvale, Calif. under the trademark “GEL-PAK”. These carriers include a plastic frame and an elastomeric membrane formulated to provide a releasable adhesive surface for the separate components. Representative elastomeric membrane materials include silicone, polyurethane, thermoplastic elastomers and polyimide. The elastomeric membrane can accommodate various components having different sizes and shapes.
Typically, the frames for this type of carrier can be stacked for enclosing and protecting the components. In addition, the frames can have a “standard” peripheral configuration, and “standard” features that permit handling by standard equipment, such as magazines and conveyor tracks. The standard features can include lugs, recesses, chamfers and other features formed integrally with the frame. One type of standard carrier is constructed according to JEDEC (Joint Electron Device Engineering Council) standards, and is known as a JEDEC tray.
One aspect of these carriers is that the components are typically placed into the carriers one component at a time. For example with wafer dicing, a pick and place vacuum mechanism can be used to individually remove each die from a film frame for placement in the carrier. Individual loading of components into carriers can be time consuming, and subjects the components to additional handling. It would be advantageous for a dicing system to transfer diced components into carriers in groups, rather than individually.
Further, although an external configuration of a carrier may be standardized, an internal configuration of the carrier is typically adapted for use with only one type of component. For example, some carriers include individual compartments sized for a particular type of component. It would be advantageous for a carrier to have the capability to handle different types and sizes of components.
The present invention is directed to a system for dicing semiconductor components in which multiple diced components can be placed in a carrier of the system at the same time. In addition, an external configuration of a carrier tray of the system is standardized, and an internal configuration can accommodate different types of components.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved method and system for dicing semiconductor components are provided. For performing the method, a substrate containing multiple semiconductor components is provided. In the illustrative embodiment the components are chip scale packages fabricated on a wafer, such as silicon, or on a panel, such as a glass filled resin. Alternately the method can be performed using bare semiconductor dice contained on a silicon wafer.
The method includes the steps of: providing an insert having an adhesive layer for retaining the substrate; separating the substrate into separate components using the insert; and then mounting the insert with the separated components thereon to a carrier tray with a standard peripheral configuration and features. Separation of the substrate can be accomplished using a conventional dicing technique such as saw cutting, liquid jetting, laser machining, or etching the substrate. Mounting of the insert to the carrier tray can be manual, or can be with vacuum handlers, or other automated equipment.
The system includes the substrate, the insert and the carrier tray. The insert includes a base with the adhesive layer formed thereon. The adhesive layer can comprise an elastomeric material, a pressure sensitive tape, or a vacuum actuated membrane. The carrier tray includes clip members and retention members for retaining one or more inserts thereon. In addition, the carrier tray has a peripheral configuration and external features constructed according to standards of an industry standard setting body, such as JEDEC. Standardized equipment, such as magazines and conveyor tracks, can thus be used for transporting and handling the carrier tray, with the inserts and diced components retained thereon. Still further, the carrier tray includes stacking ridges that permit stacking of multiple carriers.


REFERENCES:
patent: D. 387364 (1997-12-01), Boucher et al.
patent: 4711014 (1987-12-01), Althouse
patent: 4778326 (1988-10-01), Althouse et al.
patent: 5609148 (1997-03-01), Mitwalsky et al.
patent: 5674785 (1997-10-01), Akram et al.
patent: 5682061 (1997-10-01), Khandros et al.
patent: 5682731 (1997-11-01), Althouse
patent: 5685885 (1997-11-01), Khandros et al.
patent: 5718615 (1998-02-01), Boucher et al.
patent: 5739585 (1998-04-01), Akram et al.
patent: 5834162 (1998-11-01), Malba
patent: 5891295 (1999-04-01), Barringer et al.
patent: 6136137 (2000-10-01), Farnworth et al.
patent: 57-210641 (1982-12-01), None
“Standard Tray Carrier For Chip-Scale BGA Devices”, Application Note 7, Tessera, Inc., Aug. 18, 1996, pp. 1-4.

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