Electrical computers and digital processing systems: multicomput – Master/slave computer controlling – Master/slave mode selecting
Reexamination Certificate
1998-03-31
2001-01-23
Burgess, Glenton B. (Department: 2756)
Electrical computers and digital processing systems: multicomput
Master/slave computer controlling
Master/slave mode selecting
C709S221000, C709S208000, C709S222000, C714S006130, C714S013000, C714S016000, C713S001000, C713S002000, C713S002000
Reexamination Certificate
active
06178445
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to information handling systems, and, more particularly, to a system and method for determining which processor is to be the master processor in a symmetric multi-processor environment.
BACKGROUND OF THE INVENTION
In a symmetric multi-processor (SMP) system, a number of processors are connected together by means of a system bus. The system bus may be used by only one processor at a time. Other devices, such as storage and I/O devices, are also connected to the system bus. These devices, and other system resources, such as clocks, timers, direct memory access, and memory refresh controls, are shared by the processors.
During system reset, sometimes referred to as power-on-reset (POR), one of the processors is designated as the master processor. The master processor typically takes control of the system bus, and then initializes each of the other processors. The master processor also initializes the other devices in the system, and coordinates the starting of the entire system. For example, the master processor may test various parts of the system, such as memory areas. After system initialization, the master processor may designate a different processor as the master processor, or may remain the master processor. During operation of the system, the master processor may assign work to the other processors.
When a system is powered on, one of the processors is designated as the master processor. Prior art methods for determining which processor is to be the master processor are typically hardware-based methods, which can not be changed or controlled without making a hardware change. For example, in “Method to Determine a Lead Processor in a Symmetric Multi-Processor System,” IBM Technical Disclosure Bulletin, Vol. 39, No. 05, May 1996, pp. 53-54, each processor has an equal chance to become the master. A system bus arbiter determines which processor is granted access to the bus in order to read a first access register. Thus, the master selection process can not be controlled or changed without changing the hardware.
Another prior art method, “Start-Up Master Processor Selection Method For Multi-Processor Systems,” IBM Technical Disclosure Bulletin, Vol. 33, No. 4, September 1990, pp. 375-376, discloses a method based on start-up circuitry in a system resource unit. The start-up circuitry polls each processor sequentially in order to find the first processor capable of becoming the master. The master processor then informs the other processor units that they are slave processors. The master processor selection can only be controlled by changing the hardware wiring, as the master processor is always the first processor to be polled. Further, this method may not always result in a successful system initialization. If one of the processing units malfunctions, and fails to stop driving the Ready line, the start-up circuitry will never start, and the system will not come up.
Consequently, there is a need for a system and method for determining which processor is to be the master processor in an SMP environment. It would be desirable for the system and method to be controllable and changeable, without the need for any special or dedicated hardware. It would also be desirable to increase the probability that the system will always successfully select a master processor, and will initialize successfully even if one or more of the processors malfunctions.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a system and method for determining which processor is to be the master processor in a symmetric multi-processor (SMP) environment. The determination is made by boot-level code, i.e. the software program which executes first in a processor after it is brought on-line. Each processor in the SMP system is brought on-line independently of the other processors in the system, and each processor in the system can uniquely identify itself. As each processor comes on-line, it executes a series of steps. All processors in the system may be executing the steps concurrently.
As a processor comes on-line, it checks to see if a master processor has already been designated. If not, the processor checks to see if another processor, with a higher priority identifier, has identified itself as a working processor. If so, the processor commits to being a slave processor. If not, the processor indicates that it is available to be the master processor. A further check is made to ensure that only one processor has indicated that it is available to become the master processor. If the processor determines that more than one processor has indicated its availability to become the master processor, the processor de-commits, and returns to the step of checking to see if a master processor has already been designated.
The system and method of the present invention is controllable, and may be changed without changing the system hardware. Because each processor has a priority based upon its unique identifier, changes may be made by mapping each physical processor to a different logical identifier. The mapping may be stored in a non-volatile memory area.
An advantage of the present invention is that the likelihood that a particular processor will become the master processor may be increased or decreased by changing the processor's unique identifier. Thus, the system and method is controllable and changeable, without the need for any special or dedicated hardware. Another advantage of the present invention is that it increases the probability that the system will always successfully select a master processor, and will initialize successfully even if one or more of the processors malfunctions.
REFERENCES:
patent: 4580232 (1986-04-01), Dugan et al.
patent: 5404476 (1995-04-01), Kadaira
patent: 5418955 (1995-05-01), Ikeda et al.
patent: 5530946 (1996-06-01), Bouvier et al.
patent: 5764882 (1998-06-01), Shingo
IBM TDB “Method to Determine a Lead Processor in a Symmetric Multi-Processor System” vol. 39, No. 05, May 1996, pp. 53-54.
IBM TDB Start-Up Master Processor Selection Method for Multi-Processor Systems, vol. 33, No. 4, Sep. 1990, pp. 375-376.
Dawkins George John
Lee Van Hoa
Burgess Glenton B.
International Business Machines - Corporation
Leeuwen Leslie A. Van
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