Static information storage and retrieval – Read only systems – Magnetic
Reexamination Certificate
2002-01-23
2003-11-18
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Read only systems
Magnetic
C365S210130, C365S209000, C365S207000, C365S225500, C365S189070, C365S189090
Reexamination Certificate
active
06650562
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to magnetic tunnel junction (MTJ) memory devices, and, more particularly, to a system and method for determining the logic state of a memory cell in an MTJ memory device.
2. Related Art
A typical magnetic tunnel junction (MTJ) memory device includes an array of memory cells. Each of the cells is typically constructed of two layers of magnetic film, separated by a dielectric layer. The magnetization of one of the layers is alterable and the magnetization of the other layer is fixed or “pinned” in a particular direction. The magnetic film layer having alterable magnetization is typically referred to as a “data storage layer” and the magnetic film layer which is pinned is typically referred to as a “reference layer.”
Conductive traces are typically routed across the array of memory cells. These conductive traces are typically arranged in rows and columns. The conductive traces extending along the rows of the memory cells are generally referred to as “word lines” and the conductive traces extending along the columns of the memory cells are generally referred to as “bit lines.” The word lines and bit lines are typically oriented perpendicular to each other. Located at each intersection of a word line and a bit line, each memory cell stores the bit of information as an orientation of a magnetization.
Typically, the orientation of magnetization in the data storage layer aligns along an axis of the data storage layer that is commonly referred to as its “easy axis.” Typically, external magnetic fields are applied to flip the orientation of magnetization in the data storage layer along its easy axis to either a parallel or anti-parallel orientation with respect to the orientation of magnetization in the reference layer, depending on the desired logic state.
The orientation of magnetization of each memory cell will assume one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logical values of “1” and “0”, respectively. The orientation of magnetization of a selected memory cell may be changed by supplying current to a word line and a bit line crossing at the location of the selected memory cell. The currents create magnetic fields that, when combined, can switch the orientation of magnetization of the selected memory cell from parallel to anti-parallel or vice versa.
A selected magnetic memory cell is usually written by applying electrical currents to the particular word and bit lines that intersect at the selected magnetic memory cell. Typically, an electrical current applied to the particular bit line generates a magnetic field substantially aligned along the easy axis of the selected magnetic memory cell. The magnetic field aligned to the easy axis is generally referred to as a “longitudinal write field.” An electrical current applied to the particular word line typically generates a magnetic field substantially perpendicular to the easy axis of the selected magnetic memory cell.
Typically, only one selected magnetic memory cell receives both the longitudinal and the perpendicular write fields at any one time. Non-selected memory cells that are coupled to the same word line as the selected cell generally receive only the perpendicular write field. Non-selected memory cells that are coupled to the same bit line as the selected cell generally receive only the longitudinal write field.
Because the word lines and the bit lines operate in combination to switch the orientation of magnetization of the selected memory cell (i.e., to write the memory cell), the word lines and bit lines are generally referred to collectively as “write lines.” The write lines can also be used to read the logic values stored in the memory cell.
FIG. 1
is a plan view illustration of a simplified magnetic random access memory (MRAM) array, which is an exemplar MTJ memory device. The array
100
includes memory cells
120
, word lines
130
, and bit lines
132
. The word lines
130
and bit lines
132
are referred to collectively as “write lines.” The memory cells
120
are positioned at each intersection of a word line
130
and a bit line
132
. Typically, the word lines
130
and bit lines
132
are arranged in orthogonal relation to one another and the memory cells
120
are positioned between the bit lines
132
and the word lines
130
.
FIGS. 2A
,
2
B and
2
C collectively illustrate the storage of a bit of data in a single memory cell
120
of the MRAM array of FIG.
1
. As illustrated in
FIG. 2A
, the memory cell
120
includes an active magnetic data film
122
and a pinned magnetic film
124
which are separated by a dielectric region
126
. The orientation of magnetization in the active magnetic data film
122
is not fixed and can assume two stable orientations, as shown by arrow M
1
. In contrast, the pinned magnetic film
124
has a fixed orientation of magnetization, as shown by arrow M
2
. The active magnetic data film
122
rotates its orientation of magnetization in response to electrical currents applied to the write lines (i.e., the word lines
130
and bit lines
132
of
FIG. 1
) during a write operation to the memory cell
120
. The first logic state of the data bit stored in memory cell
120
is indicated when M
1
and M
2
are parallel to each other, as illustrated in FIG.
2
B. When M
1
and M
2
are parallel, a logic “1” state is stored in the memory cell
120
. Conversely, a second logic state is indicated when M
1
and M
2
are anti-parallel to each other, as illustrated in FIG.
2
C. When M
1
and M
2
are anti-parallel, a logic “0” state is stored in the memory cell
120
. In
FIGS. 2B and 2C
, the dialectic region
126
has been omitted. Although
FIGS. 2A
,
2
B and
2
C collectively illustrate the active magnetic data film
122
positioned above the pinned magnetic film
124
, the pinned magnetic film
124
alternatively may be positioned above the active magnetic data film
122
.
The resistance of the memory cell
120
differs according to the orientations of M
1
and M
2
. When M
1
and M
2
are anti-parallel (i.e., the logic “0” state), the resistance of the memory cell
120
is at its highest. On the other hand, the resistance of the memory cell
120
is at its lowest when the orientations of M
1
and M
2
are parallel (i.e., the logic “1” state). As a consequence, the logic state of the data bit stored in the memory cell
120
can be determined by measuring the current flowing through memory cell
120
.
FIG. 3
is a simplified illustration of an MTJ array
100
having a sensing circuit
150
for measuring the sense current flowing through one cell of the array
100
. The array
100
is comprised of a plurality of word lines
130
and a plurality of bit lines
132
. As described with respect to
FIG. 1
, a memory cell
120
is formed at each intersection of a word line
130
and a bit line
132
(for simplicity only the cells on the top row are numbered, but it should be understood that a cell is formed at each intersection of word lines
130
and bit lines
132
). The particular cell for which the sense current is to be measured is denoted as cell
120
a
. A bias voltage (V
a
) is applied to each of the bit lines
132
of MTJ array
100
. The same bias voltage (V
a
) is also applied to each of the word lines
130
of MTJ array
100
, with the exception of the word line that intersects cell
120
a
, which for clarity is denoted as word line
130
a
. For a symmetric array having N word lines
130
and N bit lines
132
, bias voltage V
a
would be applied to all N of the bit lines
132
and to N−1 of the word lines
130
. A second bias voltage (V
b
) is applied to the word line
130
a
that intersects cell
120
a
. Typically V
a
>V
b
and in a typical implementation, V
b
is ground potential. Thus, the biasing voltage for each of the cells
120
in the array
100
, with the exception of cell
120
a
is zero (V
a
−V
a
). The biasing voltage for cell
120
a
is (V
a
−V
b
), which results in a sense current (I
Holden Anthony
Perner Frederick A.
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